/* * SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2024 Napatech A/S */ /* * nthw_fpga_reg_defs_dbs.h * * Auto-generated file - do *NOT* edit * */ #ifndef _NTHW_FPGA_REG_DEFS_DBS_ #define _NTHW_FPGA_REG_DEFS_DBS_ /* DBS */ #define DBS_RX_AM_CTRL (0x7359feUL) #define DBS_RX_AM_CTRL_ADR (0x4704a1UL) #define DBS_RX_AM_CTRL_CNT (0x104f9d70UL) #define DBS_RX_AM_DATA (0xafa2dbe7UL) #define DBS_RX_AM_DATA_ENABLE (0x11658278UL) #define DBS_RX_AM_DATA_GPA (0xbf307344UL) #define DBS_RX_AM_DATA_HID (0x5f0669eeUL) #define DBS_RX_AM_DATA_INT (0xc32857aUL) #define DBS_RX_AM_DATA_PCKED (0x7d840fb4UL) #define DBS_RX_CONTROL (0xb18b2866UL) #define DBS_RX_CONTROL_AME (0x1f9219acUL) #define DBS_RX_CONTROL_AMS (0xeb46acfdUL) #define DBS_RX_CONTROL_LQ (0xe65f90b2UL) #define DBS_RX_CONTROL_QE (0x3e928d3UL) #define DBS_RX_CONTROL_UWE (0xb490e8dbUL) #define DBS_RX_CONTROL_UWS (0x40445d8aUL) #define DBS_RX_DR_CTRL (0xa0cbc617UL) #define DBS_RX_DR_CTRL_ADR (0xa7b57286UL) #define DBS_RX_DR_CTRL_CNT (0xb7bdeb57UL) #define DBS_RX_DR_DATA (0xf1a440eUL) #define DBS_RX_DR_DATA_GPA (0x18c20563UL) #define DBS_RX_DR_DATA_HDR (0xb98ed4d5UL) #define DBS_RX_DR_DATA_HID (0xf8f41fc9UL) #define DBS_RX_DR_DATA_PCKED (0x1e27ce2aUL) #define DBS_RX_DR_DATA_QS (0xffb980ddUL) #define DBS_RX_IDLE (0x93c723bfUL) #define DBS_RX_IDLE_BUSY (0x8e043b5bUL) #define DBS_RX_IDLE_IDLE (0x9dba27ccUL) #define DBS_RX_IDLE_QUEUE (0xbbddab49UL) #define DBS_RX_INIT (0x899772deUL) #define DBS_RX_INIT_BUSY (0x8576d90aUL) #define DBS_RX_INIT_INIT (0x8c9894fcUL) #define DBS_RX_INIT_QUEUE (0xa7bab8c9UL) #define DBS_RX_INIT_VAL (0x7789b4d8UL) #define DBS_RX_INIT_VAL_IDX (0xead0e2beUL) #define DBS_RX_INIT_VAL_PTR (0x5330810eUL) #define DBS_RX_PTR (0x628ce523UL) #define DBS_RX_PTR_PTR (0x7f834481UL) #define DBS_RX_PTR_QUEUE (0x4f3fa6d1UL) #define DBS_RX_PTR_VALID (0xbcc5ec4dUL) #define DBS_RX_UW_CTRL (0x31afc0deUL) #define DBS_RX_UW_CTRL_ADR (0x2ee4a2c9UL) #define DBS_RX_UW_CTRL_CNT (0x3eec3b18UL) #define DBS_RX_UW_DATA (0x9e7e42c7UL) #define DBS_RX_UW_DATA_GPA (0x9193d52cUL) #define DBS_RX_UW_DATA_HID (0x71a5cf86UL) #define DBS_RX_UW_DATA_INT (0x22912312UL) #define DBS_RX_UW_DATA_ISTK (0xd469a7ddUL) #define DBS_RX_UW_DATA_PCKED (0xef15c665UL) #define DBS_RX_UW_DATA_QS (0x7d422f44UL) #define DBS_RX_UW_DATA_VEC (0x55cc9b53UL) #define DBS_STATUS (0xb5f35220UL) #define DBS_STATUS_OK (0xcf09a30fUL) #define DBS_TX_AM_CTRL (0xd6d29b9UL) #define DBS_TX_AM_CTRL_ADR (0xf8854f17UL) #define DBS_TX_AM_CTRL_CNT (0xe88dd6c6UL) #define DBS_TX_AM_DATA (0xa2bcaba0UL) #define DBS_TX_AM_DATA_ENABLE (0xb6513570UL) #define DBS_TX_AM_DATA_GPA (0x47f238f2UL) #define DBS_TX_AM_DATA_HID (0xa7c42258UL) #define DBS_TX_AM_DATA_INT (0xf4f0ceccUL) #define DBS_TX_AM_DATA_PCKED (0x2e156650UL) #define DBS_TX_CONTROL (0xbc955821UL) #define DBS_TX_CONTROL_AME (0xe750521aUL) #define DBS_TX_CONTROL_AMS (0x1384e74bUL) #define DBS_TX_CONTROL_LQ (0x46ba4f6fUL) #define DBS_TX_CONTROL_QE (0xa30cf70eUL) #define DBS_TX_CONTROL_UWE (0x4c52a36dUL) #define DBS_TX_CONTROL_UWS (0xb886163cUL) #define DBS_TX_DR_CTRL (0xadd5b650UL) #define DBS_TX_DR_CTRL_ADR (0x5f773930UL) #define DBS_TX_DR_CTRL_CNT (0x4f7fa0e1UL) #define DBS_TX_DR_DATA (0x2043449UL) #define DBS_TX_DR_DATA_GPA (0xe0004ed5UL) #define DBS_TX_DR_DATA_HDR (0x414c9f63UL) #define DBS_TX_DR_DATA_HID (0x36547fUL) #define DBS_TX_DR_DATA_PCKED (0x4db6a7ceUL) #define DBS_TX_DR_DATA_PORT (0xf306968cUL) #define DBS_TX_DR_DATA_QS (0x5f5c5f00UL) #define DBS_TX_IDLE (0xf0171685UL) #define DBS_TX_IDLE_BUSY (0x61399ebbUL) #define DBS_TX_IDLE_IDLE (0x7287822cUL) #define DBS_TX_IDLE_QUEUE (0x1b387494UL) #define DBS_TX_INIT (0xea4747e4UL) #define DBS_TX_INIT_BUSY (0x6a4b7ceaUL) #define DBS_TX_INIT_INIT (0x63a5311cUL) #define DBS_TX_INIT_QUEUE (0x75f6714UL) #define DBS_TX_INIT_VAL (0x9f3c7e9bUL) #define DBS_TX_INIT_VAL_IDX (0xc82a364cUL) #define DBS_TX_INIT_VAL_PTR (0x71ca55fcUL) #define DBS_TX_PTR (0xb4d5063eUL) #define DBS_TX_PTR_PTR (0x729d34c6UL) #define DBS_TX_PTR_QUEUE (0xa0020331UL) #define DBS_TX_PTR_VALID (0x53f849adUL) #define DBS_TX_QOS_CTRL (0x3b2c3286UL) #define DBS_TX_QOS_CTRL_ADR (0x666600acUL) #define DBS_TX_QOS_CTRL_CNT (0x766e997dUL) #define DBS_TX_QOS_DATA (0x94fdb09fUL) #define DBS_TX_QOS_DATA_BS (0x2c394071UL) #define DBS_TX_QOS_DATA_EN (0x7eba6fUL) #define DBS_TX_QOS_DATA_IR (0xb8caa92cUL) #define DBS_TX_QOS_DATA_MUL (0xd7407a67UL) #define DBS_TX_QOS_RATE (0xe6e27cc5UL) #define DBS_TX_QOS_RATE_DIV (0x8cd07ba3UL) #define DBS_TX_QOS_RATE_MUL (0x9814e40bUL) #define DBS_TX_QP_CTRL (0xd5fba432UL) #define DBS_TX_QP_CTRL_ADR (0x84238184UL) #define DBS_TX_QP_CTRL_CNT (0x942b1855UL) #define DBS_TX_QP_DATA (0x7a2a262bUL) #define DBS_TX_QP_DATA_VPORT (0xda741d67UL) #define DBS_TX_UW_CTRL (0x3cb1b099UL) #define DBS_TX_UW_CTRL_ADR (0xd626e97fUL) #define DBS_TX_UW_CTRL_CNT (0xc62e70aeUL) #define DBS_TX_UW_DATA (0x93603280UL) #define DBS_TX_UW_DATA_GPA (0x69519e9aUL) #define DBS_TX_UW_DATA_HID (0x89678430UL) #define DBS_TX_UW_DATA_INO (0x5036a148UL) #define DBS_TX_UW_DATA_INT (0xda5368a4UL) #define DBS_TX_UW_DATA_ISTK (0xf693732fUL) #define DBS_TX_UW_DATA_PCKED (0xbc84af81UL) #define DBS_TX_UW_DATA_QS (0xdda7f099UL) #define DBS_TX_UW_DATA_VEC (0xad0ed0e5UL) #endif /* _NTHW_FPGA_REG_DEFS_DBS_ */ /* * Auto-generated file - do *NOT* edit */