Lines Matching refs:state
723 * Initial state: CC.EN = 1, CSTS.RDY = 0
731 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
732 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
736 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1);
744 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_EN_0);
746 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
754 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
760 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
766 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
774 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
779 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
795 * Initial state: CC.EN = 1, CSTS.RDY = 1
804 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
805 while (ctrlr.state != NVME_CTRLR_STATE_SET_EN_0) {
809 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
817 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
823 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
829 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
837 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
842 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
858 * Initial state: CC.EN = 0, CSTS.RDY = 0
878 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
879 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
883 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
885 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
887 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
889 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
901 * Reset to initial state
914 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
915 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
919 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
921 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
923 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
934 * Reset to initial state
947 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
948 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
952 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
954 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
956 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
967 * Reset to initial state
980 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
981 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
985 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
987 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
989 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1000 * Reset to initial state
1013 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1014 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1018 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1020 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1022 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1024 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1034 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
1039 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
1055 * Initial state: CC.EN = 0, CSTS.RDY = 0
1075 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1076 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1080 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1082 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1084 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1086 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1098 * Reset to initial state
1111 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1112 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1116 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1118 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1120 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1122 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1134 * Reset to initial state
1147 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1148 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1152 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1154 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1156 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1167 * Reset to initial state
1180 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1181 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1185 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1187 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1189 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1200 * Reset to initial state
1213 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1214 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1218 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1220 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1222 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1224 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1234 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
1239 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
1254 * Initial state: CC.EN = 0, CSTS.RDY = 0
1274 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1275 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1279 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1281 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1283 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1285 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1297 * Reset to initial state
1310 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1311 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1315 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1317 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1319 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1330 * Reset to initial state
1343 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1344 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1348 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1350 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1352 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1354 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1366 * Reset to initial state
1379 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1380 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1384 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1386 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1388 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1399 * Reset to initial state
1412 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1413 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1417 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1419 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1421 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1423 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1433 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
1438 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
1454 * Initial state: CC.EN = 0, CSTS.RDY = 0
1463 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1464 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1468 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1471 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1474 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1477 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1485 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
1490 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
1506 * Initial state: CC.EN = 0, CSTS.RDY = 1
1514 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
1515 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
1519 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
1526 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
1532 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
1538 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
1546 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
1551 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
1569 ctrlr->state = NVME_CTRLR_STATE_READY;
1635 /* IO qpair can only be created when ctrlr is in READY state */
1636 ctrlr.state = NVME_CTRLR_STATE_ENABLE;
1639 ctrlr.state = NVME_CTRLR_STATE_READY;
1786 qpair->state = NVME_QPAIR_CONNECTED;
1834 qpair.state = NVME_QPAIR_CONNECTED;
1841 qpair.state = NVME_QPAIR_DISCONNECTED;
1940 ctrlr.state = NVME_CTRLR_STATE_SET_HOST_FEATURE;
1943 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_DB_BUF_CFG);
1946 ctrlr.state = NVME_CTRLR_STATE_SET_HOST_FEATURE;
1948 while (ctrlr.state != NVME_CTRLR_STATE_SET_DB_BUF_CFG) {
2202 ctrlr.state = NVME_CTRLR_STATE_READY;
2282 struct spdk_nvme_ctrlr ctrlr = {.state = NVME_CTRLR_STATE_READY};
2304 * Initial state: CC.EN = 0, CSTS.RDY = 0
2318 ctrlr.state = NVME_CTRLR_STATE_INIT_DELAY;
2320 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
2326 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT);
2331 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) {
2335 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
2338 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);
2341 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE);
2344 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1);
2352 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE);
2357 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
2415 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2417 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2419 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2421 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2423 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2425 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2427 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2438 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2440 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2442 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2444 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2446 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2448 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2450 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2463 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2465 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2467 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2469 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2471 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2473 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2475 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2488 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2490 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2492 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2494 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2496 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2498 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2500 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2513 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2515 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2517 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2519 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2521 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2523 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2525 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2536 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2538 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2540 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2542 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2544 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2546 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2548 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2567 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY;
2569 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER);
2571 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2573 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2575 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES);
2581 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS);
2597 ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT;
2600 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2607 ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT;
2610 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC);
2617 ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT;
2620 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR);
2707 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2711 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2718 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT);
2735 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2737 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2768 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2770 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2787 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2791 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2810 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2812 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS);
2845 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2848 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
2904 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS;
2907 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
2925 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
2970 ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER;
2973 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
3017 ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER;
3021 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
3072 /* case 1: No first/next active NS, move on to the next state, expect: pass */
3078 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES);
3082 memset(&ctrlr.state, 0x00, sizeof(ctrlr.state));
3093 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES);
3097 memset(&ctrlr.state, 0x00, sizeof(ctrlr.state));
3113 CU_ASSERT(ctrlr.state == 0);
3115 CU_ASSERT(ns_ctrlr[4].state == NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC);
3123 memset(&ctrlr.state, 0x00, sizeof(ctrlr.state));
3131 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR);
3172 ctrlr.state = NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES;
3175 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES);
3179 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES);
3226 * Each ANA group has a namespace and has a different ANA state.
3313 ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER;
3326 /* Bring controller to ready state */
3327 while (ctrlr.state != NVME_CTRLR_STATE_READY) {
3385 ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY;
3387 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
3390 ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY;
3393 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR);
3405 ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY;
3407 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY);
3417 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0);
3423 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED);