Lines Matching defs:header
61 vmd_device_is_enumerated(volatile struct pci_header *header)
63 return header->one.prefetch_base_upper == VMD_UPPER_BASE_SIGNATURE &&
64 header->one.prefetch_limit_upper == VMD_UPPER_LIMIT_SIGNATURE;
68 vmd_device_is_root_port(volatile struct pci_header *header)
70 return header->common.vendor_id == SPDK_PCI_VID_INTEL &&
71 (header->common.device_id == PCI_ROOT_PORT_A_INTEL_SKX ||
72 header->common.device_id == PCI_ROOT_PORT_B_INTEL_SKX ||
73 header->common.device_id == PCI_ROOT_PORT_C_INTEL_SKX ||
74 header->common.device_id == PCI_ROOT_PORT_D_INTEL_SKX ||
75 header->common.device_id == PCI_ROOT_PORT_A_INTEL_ICX ||
76 header->common.device_id == PCI_ROOT_PORT_B_INTEL_ICX ||
77 header->common.device_id == PCI_ROOT_PORT_C_INTEL_ICX ||
78 header->common.device_id == PCI_ROOT_PORT_D_INTEL_ICX);
236 return (dev && dev->header) &&
237 ((dev->header->common.header_type & ~PCI_MULTI_FUNCTION) == PCI_HEADER_TYPE_NORMAL);
250 if (dev->header->common.header_type == PCI_HEADER_TYPE_BRIDGE) {
257 SPDK_INFOLOG(vmd, "base:limit = %x:%x\n", bridge->header->one.mem_base,
258 bridge->header->one.mem_limit);
268 if (bridge->header->one.mem_base > base) {
269 bridge->header->one.mem_base = base;
270 base = bridge->header->one.mem_base;
273 if (bridge->header->one.mem_limit < limit) {
274 bridge->header->one.mem_limit = limit;
275 limit = bridge->header->one.mem_limit;
288 return dev->header->zero.BAR[index] & ~0xf;
293 return (uint64_t)bus->self->header->one.mem_base << 16;
321 bar_value = dev->header->zero.BAR[i];
322 dev->header->zero.BAR[i] = ~(0U);
323 dev->bar[i].size = dev->header->zero.BAR[i];
324 dev->header->zero.BAR[i] = bar_value;
327 dev->header->zero.BAR[i] & 1) {
340 dev->header->zero.BAR[i] = (uint32_t)dev->bar[i].start;
350 mem_limit = BRIDGE_BASEREG(dev->header->zero.BAR[i]) +
353 mem_base = BRIDGE_BASEREG(dev->header->zero.BAR[i]);
361 dev->header->zero.BAR[i] = (uint32_t)(dev->bar[i].start >> PCI_DWORD_SHIFT);
367 dev->header->zero.command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
372 { uint16_t cmd = dev->header->zero.command; (void)cmd; }
397 config_space = (volatile uint8_t *)dev->header;
398 if ((dev->header->common.status & PCI_CAPABILITIES_LIST) == 0) {
402 capabilities_offset = dev->header->zero.cap_pointer;
403 if (dev->header->common.header_type & PCI_HEADER_TYPE_BRIDGE) {
404 capabilities_offset = dev->header->one.cap_pointer;
438 data = (uint8_t *)dev->header;
460 dev->header->common.command |= (BUS_MASTER_ENABLE | MEMORY_SPACE_ENABLE);
461 { uint16_t cmd = dev->header->common.command; (void)cmd; }
481 if (vmd_device_is_root_port(dev->header)) {
486 dev->header->one.prefetch_base_upper,
487 dev->header->one.prefetch_limit_upper);
488 if (vmd_device_is_enumerated(dev->header)) {
497 vmd_reset_base_limit_registers(volatile struct pci_header *header)
507 header->one.mem_base = 0xfff0;
508 reg = header->one.mem_base;
509 header->one.mem_limit = 0x0;
510 reg = header->one.mem_limit;
511 header->one.prefetch_base = 0x0;
512 reg = header->one.prefetch_base;
513 header->one.prefetch_limit = 0x0;
514 reg = header->one.prefetch_limit;
515 header->one.prefetch_base_upper = 0x0;
516 reg = header->one.prefetch_base_upper;
517 header->one.prefetch_limit_upper = 0x0;
518 reg = header->one.prefetch_limit_upper;
519 header->one.io_base_upper = 0x0;
520 reg = header->one.io_base_upper;
521 header->one.io_limit_upper = 0x0;
522 reg = header->one.io_limit_upper;
523 header->one.primary = 0;
524 reg = header->one.primary;
525 header->one.secondary = 0;
526 reg = header->one.secondary;
527 header->one.subordinate = 0;
528 reg = header->one.subordinate;
543 bus->self->header->one.mem_base = BRIDGE_BASEREG(hp->bar.start);
544 bus->self->header->one.mem_limit =
545 bus->self->header->one.mem_base + BRIDGE_BASEREG(hp->bar.size - 1);
547 hp->bar.start = (uint64_t)bus->self->header->one.mem_base << 16;
566 bus->self->header->one.mem_base, bus->self->header->one.mem_limit);
572 volatile struct pci_header *header;
574 header = (volatile struct pci_header *)(bus->vmd->cfg_vaddr +
576 if (!vmd_is_valid_cfg_addr(bus, (uint64_t)header)) {
580 if (header->common.vendor_id == PCI_INVALID_VENDORID || header->common.vendor_id == 0x0) {
591 struct pci_header volatile *header;
606 header = (struct pci_header * volatile)(bus->vmd->cfg_vaddr +
610 header->common.vendor_id, header->common.device_id);
617 dev->header = header;
618 dev->vid = dev->header->common.vendor_id;
619 dev->did = dev->header->common.device_id;
623 header_type = dev->header->common.header_type;
624 rev_class = dev->header->common.rev_class;
631 vmd_reset_base_limit_registers(dev->header);
757 subordinate_bus = bridge->header->one.subordinate;
760 if (dev->header->one.subordinate < subordinate_bus) {
761 dev->header->one.subordinate = subordinate_bus;
762 subordinate_bus = dev->header->one.subordinate;
797 volatile uint8_t *src = (volatile uint8_t *)dev->header;
817 volatile uint8_t *dst = (volatile uint8_t *)dev->header;
870 dev->pci.id.vendor_id = dev->header->common.vendor_id;
871 dev->pci.id.device_id = dev->header->common.device_id;
929 * 0 and 1 header.
943 * Return count of how many devices found(type1 + type 0 header devices)
962 if (new_dev->header->common.header_type & PCI_HEADER_TYPE_BRIDGE) {
1000 new_dev->header->one.primary = new_bus->primary_bus;
1001 new_dev->header->one.secondary = new_bus->secondary_bus;
1002 new_dev->header->one.subordinate = new_bus->subordinate_bus;
1043 dev->header->common.vendor_id, dev->header->common.device_id,
1048 dev->header->common.vendor_id, dev->header->common.device_id);
1056 dev->header->zero.BAR[0], (void *)dev->bar[0].vaddr);
1061 dev->header->one.primary, dev->header->one.secondary, dev->header->one.subordinate);
1088 SPDK_INFOLOG(vmd, "vendor/device id:%x:%x\n", dev->header->common.vendor_id,
1089 dev->header->common.device_id);
1091 if (vmd_device_is_root_port(dev->header)) {
1092 dev->header->one.prefetch_base_upper = VMD_UPPER_BASE_SIGNATURE;
1093 reg = dev->header->one.prefetch_base_upper;
1094 dev->header->one.prefetch_limit_upper = VMD_UPPER_LIMIT_SIGNATURE;
1095 reg = dev->header->one.prefetch_limit_upper;
1098 dev->header->one.prefetch_base_upper,
1099 dev->header->one.prefetch_limit_upper);
1106 volatile struct pci_header *header;
1122 header = (volatile void *)(bus->vmd->cfg_vaddr +
1124 if (vmd_device_is_root_port(header) && !vmd_device_is_enumerated(header)) {
1125 vmd_reset_base_limit_registers(header);
1514 if (dev->header->common.header_type & PCI_HEADER_TYPE_BRIDGE) {