Lines Matching defs:bits

157 		} bits;
243 	treq->ordering.bits.in_progress_accel = 1;
526 	assert(treq->ordering.bits.in_progress_accel);
527 	treq->ordering.bits.in_progress_accel = 0;
619 	assert(treq->ordering.bits.in_progress_accel);
620 	treq->ordering.bits.in_progress_accel = 0;
701 	if (!tcp_req->ordering.bits.domain_in_use) {
810 	tcp_req->ordering.bits.domain_in_use = (req->payload.opts && req->payload.opts->memory_domain);
865 	if (!(tcp_req->ordering.bits.send_ack && tcp_req->ordering.bits.data_recv &&
866 	      !tcp_req->ordering.bits.in_progress_accel)) {
885 	tcp_req->ordering.bits.send_ack = 1;
887 	if (spdk_unlikely(tcp_req->ordering.bits.h2c_send_waiting_ack)) {
891 		if (tcp_req->in_capsule_data && tcp_req->ordering.bits.domain_in_use) {
1054 		if (tcp_req->ordering.bits.in_progress_accel) {
1229 	assert(treq->ordering.bits.in_progress_accel);
1230 	treq->ordering.bits.in_progress_accel = 0;
1270 			tcp_req->ordering.bits.data_recv = 1;
1499 	tqpair->flags.host_hdgst_enable = ic_resp->dgst.bits.hdgst_enable ? true : false;
1500 	tqpair->flags.host_ddgst_enable = ic_resp->dgst.bits.ddgst_enable ? true : false;
1562 	tcp_req->ordering.bits.data_recv = 1;
1697 	tcp_req->ordering.bits.send_ack = 1;
1705 		if (tcp_req->ordering.bits.r2t_waiting_h2c_complete) {
1706 			tcp_req->ordering.bits.r2t_waiting_h2c_complete = 0;
1716 		if (tcp_req->ordering.bits.domain_in_use) {
1734 	/* Reinit the send_ack and h2c_send_waiting_ack bits */
1735 	tcp_req->ordering.bits.send_ack = 0;
1736 	tcp_req->ordering.bits.h2c_send_waiting_ack = 0;
1830 		if (tcp_req->state == NVME_TCP_REQ_ACTIVE_R2T && !tcp_req->ordering.bits.send_ack) {
1836 			tcp_req->ordering.bits.r2t_waiting_h2c_complete = 1;
1851 	if (spdk_likely(tcp_req->ordering.bits.send_ack)) {
1854 		tcp_req->ordering.bits.h2c_send_waiting_ack = 1;
2198 	ic_req->dgst.bits.hdgst_enable = tqpair->qpair.ctrlr->opts.header_digest;
2199 	ic_req->dgst.bits.ddgst_enable = tqpair->qpair.ctrlr->opts.data_digest;