Lines Matching full:temp
458 temp: .EQU r1 label
478 sub r0,arg1,temp ; clear carry, negate the divisor
479 ds r0,temp,r0 ; set V-bit to 1
482 ds r0,arg1,temp ; 1st divide step, if no carry
484 ds temp,arg1,temp ; 2nd divide step
486 ds temp,arg1,temp ; 3rd divide step
488 ds temp,arg1,temp ; 4th divide step
490 ds temp,arg1,temp ; 5th divide step
492 ds temp,arg1,temp ; 6th divide step
494 ds temp,arg1,temp ; 7th divide step
496 ds temp,arg1,temp ; 8th divide step
498 ds temp,arg1,temp ; 9th divide step
500 ds temp,arg1,temp ; 10th divide step
502 ds temp,arg1,temp ; 11th divide step
504 ds temp,arg1,temp ; 12th divide step
506 ds temp,arg1,temp ; 13th divide step
508 ds temp,arg1,temp ; 14th divide step
510 ds temp,arg1,temp ; 15th divide step
512 ds temp,arg1,temp ; 16th divide step
514 ds temp,arg1,temp ; 17th divide step
516 ds temp,arg1,temp ; 18th divide step
518 ds temp,arg1,temp ; 19th divide step
520 ds temp,arg1,temp ; 20th divide step
522 ds temp,arg1,temp ; 21st divide step
524 ds temp,arg1,temp ; 22nd divide step
526 ds temp,arg1,temp ; 23rd divide step
528 ds temp,arg1,temp ; 24th divide step
530 ds temp,arg1,temp ; 25th divide step
532 ds temp,arg1,temp ; 26th divide step
534 ds temp,arg1,temp ; 27th divide step
536 ds temp,arg1,temp ; 28th divide step
538 ds temp,arg1,temp ; 29th divide step
540 ds temp,arg1,temp ; 30th divide step
542 ds temp,arg1,temp ; 31st divide step
544 ds temp,arg1,temp ; 32nd divide step,
577 ds r0,temp,r0 ; set V-bit to 1
581 ds r0,temp,r0 ; set V-bit to 1
965 add arg0,arg0,temp ; shift msb bit into carry
967 addc temp,temp,temp ; shift temp with/into carry
969 addc temp,temp,temp ; shift temp with/into carry
971 addc temp,temp,temp ; shift temp with/into carry
973 addc temp,temp,temp ; shift temp with/into carry
975 addc temp,temp,temp ; shift temp with/into carry
977 addc temp,temp,temp ; shift temp with/into carry
979 addc temp,temp,temp ; shift temp with/into carry
981 addc temp,temp,temp ; shift temp with/into carry
983 addc temp,temp,temp ; shift temp with/into carry
985 addc temp,temp,temp ; shift temp with/into carry
987 addc temp,temp,temp ; shift temp with/into carry
989 addc temp,temp,temp ; shift temp with/into carry
991 addc temp,temp,temp ; shift temp with/into carry
993 addc temp,temp,temp ; shift temp with/into carry
995 addc temp,temp,temp ; shift temp with/into carry
997 addc temp,temp,temp ; shift temp with/into carry
999 addc temp,temp,temp ; shift temp with/into carry
1001 addc temp,temp,temp ; shift temp with/into carry
1003 addc temp,temp,temp ; shift temp with/into carry
1005 addc temp,temp,temp ; shift temp with/into carry
1007 addc temp,temp,temp ; shift temp with/into carry
1009 addc temp,temp,temp ; shift temp with/into carry
1011 addc temp,temp,temp ; shift temp with/into carry
1013 addc temp,temp,temp ; shift temp with/into carry
1015 addc temp,temp,temp ; shift temp with/into carry
1017 addc temp,temp,temp ; shift temp with/into carry
1019 addc temp,temp,temp ; shift temp with/into carry
1021 addc temp,temp,temp ; shift temp with/into carry
1023 addc temp,temp,temp ; shift temp with/into carry
1025 addc temp,temp,temp ; shift temp with/into carry
1027 addc temp,temp,temp ; shift temp with/into carry
1696 sub 0,arg1,temp ; clear carry,
1698 ds 0,temp,0 ; set V-bit to the comple-
1701 ds r0,arg1,temp ; 1st divide step, if no carry
1703 ds temp,arg1,temp ; 2nd divide step
1705 ds temp,arg1,temp ; 3rd divide step
1707 ds temp,arg1,temp ; 4th divide step
1709 ds temp,arg1,temp ; 5th divide step
1711 ds temp,arg1,temp ; 6th divide step
1713 ds temp,arg1,temp ; 7th divide step
1715 ds temp,arg1,temp ; 8th divide step
1717 ds temp,arg1,temp ; 9th divide step
1719 ds temp,arg1,temp ; 10th divide step
1721 ds temp,arg1,temp ; 11th divide step
1723 ds temp,arg1,temp ; 12th divide step
1725 ds temp,arg1,temp ; 13th divide step
1727 ds temp,arg1,temp ; 14th divide step
1729 ds temp,arg1,temp ; 15th divide step
1731 ds temp,arg1,temp ; 16th divide step
1733 ds temp,arg1,temp ; 17th divide step
1735 ds temp,arg1,temp ; 18th divide step
1737 ds temp,arg1,temp ; 19th divide step
1739 ds temp,arg1,temp ; 20th divide step
1741 ds temp,arg1,temp ; 21st divide step
1743 ds temp,arg1,temp ; 22nd divide step
1745 ds temp,arg1,temp ; 23rd divide step
1747 ds temp,arg1,temp ; 24th divide step
1749 ds temp,arg1,temp ; 25th divide step
1751 ds temp,arg1,temp ; 26th divide step
1753 ds temp,arg1,temp ; 27th divide step
1755 ds temp,arg1,temp ; 28th divide step
1757 ds temp,arg1,temp ; 29th divide step
1759 ds temp,arg1,temp ; 30th divide step
1761 ds temp,arg1,temp ; 31st divide step
1763 ds temp,arg1,temp ; 32nd divide step,