Lines Matching defs:dci

62 	uint8_t			dci;
833 uint8_t dci, slot, code, xfertype;
838 dci = XHCI_TRB_GET_EP(flags);
844 xp = sc->sc_sdevs[slot].pipes[dci - 1];
846 DPRINTF(("%s: incorrect dci (%u)\n", DEVNAME(sc), dci));
896 code, slot, dci))
937 uint8_t code, uint8_t slot, uint8_t dci)
1004 xhci_cmd_reset_ep_async(sc, slot, dci);
1112 uint8_t dci, slot;
1131 dci = XHCI_TRB_GET_EP(flags);
1135 xp = sc->sc_sdevs[slot].pipes[dci - 1];
1140 xhci_cmd_set_tr_deq_async(sc, xp->slot, xp->dci,
1144 xp = sc->sc_sdevs[slot].pipes[dci - 1];
1340 xp->dci = xhci_ed2dci(ed);
1472 return XHCI_SCTX_DCI(lxp->dci);
1529 sdev->ep_ctx[xp->dci-1]->info_lo = htole32(xhci_pipe_interval(pipe));
1530 sdev->ep_ctx[xp->dci-1]->info_hi = htole32(
1535 sdev->ep_ctx[xp->dci-1]->txinfo = htole32(xhci_get_txinfo(sc, pipe));
1536 sdev->ep_ctx[xp->dci-1]->deqp = htole64(
1542 sdev->input_ctx->add_flags = htole32(XHCI_INCTX_MASK_DCI(xp->dci));
1609 printf("%s: pipe=%p addr=%d depth=%d port=%d speed=%d dev %d dci %u"
1611 dev->powersrc->portno, dev->speed, xp->slot, xp->dci,
1621 sdev->pipes[xp->dci - 1] = xp;
1627 if (xp->dci == 1) {
1664 sdev->input_ctx->drop_flags = htole32(XHCI_INCTX_MASK_DCI(xp->dci));
1672 memset(sdev->ep_ctx[xp->dci - 1], 0, sizeof(struct xhci_epctx));
1678 DPRINTF(("%s: error clearing ep (%d)\n", DEVNAME(sc), xp->dci));
1681 sdev->pipes[xp->dci - 1] = NULL;
1687 if (xp->dci == 1) {
1711 KASSERT(xp->dci == 1);
2077 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t slot, uint8_t dci)
2082 DPRINTF(("%s: %s dev %u dci %u\n", DEVNAME(sc), __func__, slot, dci));
2087 XHCI_TRB_SET_SLOT(slot) | XHCI_TRB_SET_EP(dci) | XHCI_CMD_STOP_EP
2097 xhci_cmd_reset_ep_async(struct xhci_softc *sc, uint8_t slot, uint8_t dci)
2101 DPRINTF(("%s: %s dev %u dci %u\n", DEVNAME(sc), __func__, slot, dci));
2106 XHCI_TRB_SET_SLOT(slot) | XHCI_TRB_SET_EP(dci) | XHCI_CMD_RESET_EP
2113 xhci_cmd_set_tr_deq_async(struct xhci_softc *sc, uint8_t slot, uint8_t dci,
2118 DPRINTF(("%s: %s dev %u dci %u\n", DEVNAME(sc), __func__, slot, dci));
2123 XHCI_TRB_SET_SLOT(slot) | XHCI_TRB_SET_EP(dci) | XHCI_CMD_SET_TR_DEQ
2364 if (xhci_cmd_stop_ep(sc, xp->slot, xp->dci)) {
2392 xhci_cmd_set_tr_deq_async(sc, xp->slot, xp->dci,
3000 XDWRITE4(sc, XHCI_DOORBELL(xp->slot), xp->dci);
3134 XDWRITE4(sc, XHCI_DOORBELL(xp->slot), xp->dci);
3324 XDWRITE4(sc, XHCI_DOORBELL(xp->slot), xp->dci);