Lines Matching defs:sc
96 #define urtw_read8_m(sc, val, data) do { \
97 error = urtw_read8_c(sc, val, data, 0); \
101 #define urtw_read8_idx_m(sc, val, data, idx) do { \
102 error = urtw_read8_c(sc, val, data, idx); \
106 #define urtw_write8_m(sc, val, data) do { \
107 error = urtw_write8_c(sc, val, data, 0); \
111 #define urtw_write8_idx_m(sc, val, data, idx) do { \
112 error = urtw_write8_c(sc, val, data, idx); \
116 #define urtw_read16_m(sc, val, data) do { \
117 error = urtw_read16_c(sc, val, data, 0); \
121 #define urtw_read16_idx_m(sc, val, data, idx) do { \
122 error = urtw_read16_c(sc, val, data, idx); \
126 #define urtw_write16_m(sc, val, data) do { \
127 error = urtw_write16_c(sc, val, data, 0); \
131 #define urtw_write16_idx_m(sc, val, data, idx) do { \
132 error = urtw_write16_c(sc, val, data, idx); \
136 #define urtw_read32_m(sc, val, data) do { \
137 error = urtw_read32_c(sc, val, data, 0); \
141 #define urtw_read32_idx_m(sc, val, data, idx) do { \
142 error = urtw_read32_c(sc, val, data, idx); \
146 #define urtw_write32_m(sc, val, data) do { \
147 error = urtw_write32_c(sc, val, data, 0); \
151 #define urtw_write32_idx_m(sc, val, data, idx) do { \
152 error = urtw_write32_c(sc, val, data, idx); \
156 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \
157 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
161 #define urtw_8187_write_phy_cck(sc, val, data) do { \
162 error = urtw_8187_write_phy_cck_c(sc, val, data); \
166 #define urtw_8225_write(sc, val, data) do { \
167 error = urtw_8225_write_c(sc, val, data); \
592 struct urtw_softc *sc = (struct urtw_softc *)self;
594 struct ieee80211com *ic = &sc->sc_ic;
601 sc->sc_udev = uaa->device;
602 sc->sc_iface = uaa->iface;
603 sc->sc_hwrev = urtw_lookup(uaa->vendor, uaa->product)->rev;
605 printf("%s: ", sc->sc_dev.dv_xname);
607 if (sc->sc_hwrev & URTW_HWREV_8187) {
608 urtw_read32_m(sc, URTW_TX_CONF, &data);
612 sc->sc_hwrev |= URTW_HWREV_8187_D;
620 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B;
624 sc->sc_hwrev |= URTW_HWREV_8187_B;
630 urtw_read8_m(sc, URTW_8187B_HWREV, &data8);
633 sc->sc_hwrev |= URTW_HWREV_8187B_B;
637 sc->sc_hwrev |= URTW_HWREV_8187B_D;
641 sc->sc_hwrev |= URTW_HWREV_8187B_E;
645 sc->sc_hwrev |= URTW_HWREV_8187B_B;
651 urtw_read32_m(sc, URTW_RX, &data);
652 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
655 error = urtw_get_rfchip(sc);
658 error = urtw_get_macaddr(sc);
661 error = urtw_get_txpwr(sc);
664 error = urtw_led_init(sc); /* XXX incomplete */
668 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY;
669 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY;
670 sc->sc_currate = 3;
672 sc->sc_preamble_mode = 2;
674 usb_init_task(&sc->sc_task, urtw_task, sc, USB_TASK_TYPE_GENERIC);
675 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc,
677 timeout_set(&sc->scan_to, urtw_next_scan, sc);
678 timeout_set(&sc->sc_led_ch, urtw_ledtask, sc);
706 ifp->if_softc = sc;
708 if (sc->sc_hwrev & URTW_HWREV_8187) {
709 sc->sc_init = urtw_init;
711 sc->sc_init = urtw_8187b_init;
716 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
722 sc->sc_newstate = ic->ic_newstate;
727 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO,
730 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
731 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
732 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT);
734 sc->sc_txtap_len = sizeof sc->sc_txtapu;
735 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
736 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT);
749 struct urtw_softc *sc = (struct urtw_softc *)self;
750 struct ifnet *ifp = &sc->sc_ic.ic_if;
755 if (timeout_initialized(&sc->scan_to))
756 timeout_del(&sc->scan_to);
757 if (timeout_initialized(&sc->sc_led_ch))
758 timeout_del(&sc->sc_led_ch);
760 usb_rem_wait_task(sc->sc_udev, &sc->sc_task);
761 usb_rem_wait_task(sc->sc_udev, &sc->sc_ledtask);
763 usbd_ref_wait(sc->sc_udev);
771 urtw_free_tx_data_list(sc);
772 urtw_free_rx_data_list(sc);
773 urtw_close_pipes(sc);
781 urtw_close_pipes(struct urtw_softc *sc)
785 if (sc->sc_rxpipe != NULL) {
786 error = usbd_close_pipe(sc->sc_rxpipe);
789 sc->sc_rxpipe = NULL;
791 if (sc->sc_txpipe_low != NULL) {
792 error = usbd_close_pipe(sc->sc_txpipe_low);
795 sc->sc_txpipe_low = NULL;
797 if (sc->sc_txpipe_normal != NULL) {
798 error = usbd_close_pipe(sc->sc_txpipe_normal);
801 sc->sc_txpipe_normal = NULL;
808 urtw_open_pipes(struct urtw_softc *sc)
818 if (sc->sc_hwrev & URTW_HWREV_8187)
819 error = usbd_open_pipe(sc->sc_iface, 0x2,
820 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low);
822 error = usbd_open_pipe(sc->sc_iface, 0x6,
823 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low);
826 sc->sc_dev.dv_xname, usbd_errstr(error));
830 if (sc->sc_hwrev & URTW_HWREV_8187)
831 error = usbd_open_pipe(sc->sc_iface, 0x3,
832 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal);
834 error = usbd_open_pipe(sc->sc_iface, 0x7,
835 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal);
838 sc->sc_dev.dv_xname, usbd_errstr(error));
842 if (sc->sc_hwrev & URTW_HWREV_8187)
843 error = usbd_open_pipe(sc->sc_iface, 0x81,
844 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe);
846 error = usbd_open_pipe(sc->sc_iface, 0x83,
847 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe);
850 sc->sc_dev.dv_xname, usbd_errstr(error));
856 (void)urtw_close_pipes(sc);
861 urtw_alloc_rx_data_list(struct urtw_softc *sc)
866 struct urtw_rx_data *data = &sc->sc_rx_data[i];
868 data->sc = sc;
870 data->xfer = usbd_alloc_xfer(sc->sc_udev);
873 sc->sc_dev.dv_xname);
880 sc->sc_dev.dv_xname);
888 sc->sc_dev.dv_xname);
895 sc->sc_dev.dv_xname);
905 urtw_free_rx_data_list(sc);
910 urtw_free_rx_data_list(struct urtw_softc *sc)
915 if (sc->sc_rxpipe != NULL)
916 usbd_abort_pipe(sc->sc_rxpipe);
919 struct urtw_rx_data *data = &sc->sc_rx_data[i];
933 urtw_alloc_tx_data_list(struct urtw_softc *sc)
938 struct urtw_tx_data *data = &sc->sc_tx_data[i];
940 data->sc = sc;
943 data->xfer = usbd_alloc_xfer(sc->sc_udev);
946 sc->sc_dev.dv_xname);
954 sc->sc_dev.dv_xname);
961 sc->sc_dev.dv_xname, data->buf);
967 urtw_free_tx_data_list(sc);
972 urtw_free_tx_data_list(struct urtw_softc *sc)
974 struct ieee80211com *ic = &sc->sc_ic;
978 if (sc->sc_txpipe_low != NULL)
979 usbd_abort_pipe(sc->sc_txpipe_low);
980 if (sc->sc_txpipe_normal != NULL)
981 usbd_abort_pipe(sc->sc_txpipe_normal);
984 struct urtw_tx_data *data = &sc->sc_tx_data[i];
1000 struct urtw_softc *sc = ifp->if_softc;
1008 error = sc->sc_init(ifp);
1016 struct urtw_softc *sc = ic->ic_if.if_softc;
1018 usb_rem_task(sc->sc_udev, &sc->sc_task);
1019 timeout_del(&sc->scan_to);
1022 sc->sc_state = nstate;
1023 sc->sc_arg = arg;
1024 usb_add_task(sc->sc_udev, &sc->sc_task);
1030 urtw_led_init(struct urtw_softc *sc)
1035 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
1036 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
1042 sc->sc_strategy = URTW_SW_LED_MODE1;
1045 sc->sc_strategy = URTW_SW_LED_MODE3;
1048 sc->sc_strategy = URTW_HW_LED;
1053 sc->sc_strategy = URTW_SW_LED_MODE0;
1057 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
1064 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index,
1076 return (usbd_do_request(sc->sc_udev, &req, &data));
1080 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
1090 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
1091 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
1092 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
1093 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf);
1094 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf);
1096 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
1098 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
1104 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
1106 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
1109 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
1116 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
1119 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
1122 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
1125 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
1128 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
1130 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
1135 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
1138 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
1141 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
1144 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
1148 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
1150 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
1155 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
1159 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
1160 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
1161 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0);
1170 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
1175 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
1177 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
1178 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
1180 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007);
1181 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007);
1184 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
1186 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
1189 error = urtw_8225_write_s16(sc, addr, 0x8225, data);
1193 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
1195 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
1196 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
1197 usbd_delay_ms(sc->sc_udev, 2);
1203 urtw_8225_isv2(struct urtw_softc *sc, int *ret)
1210 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080);
1211 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080);
1212 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080);
1213 usbd_delay_ms(sc->sc_udev, 500);
1215 urtw_8225_write(sc, 0x0, 0x1b7);
1217 error = urtw_8225_read(sc, 0x8, &data);
1223 error = urtw_8225_read(sc, 0x9, &data);
1230 urtw_8225_write(sc, 0x0, 0xb7);
1236 urtw_get_rfchip(struct urtw_softc *sc)
1238 struct urtw_rf *rf = &sc->sc_rf;
1243 rf->rf_sc = sc;
1245 if (sc->sc_hwrev & URTW_HWREV_8187) {
1246 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
1251 error = urtw_8225_isv2(sc, &ret);
1286 urtw_get_txpwr(struct urtw_softc *sc)
1292 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
1295 sc->sc_txpwr_cck_base = data & 0xf;
1296 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
1299 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
1302 sc->sc_txpwr_cck[i] = data & 0xf;
1303 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
1304 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
1305 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
1308 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
1311 sc->sc_txpwr_cck[i + 6] = data & 0xf;
1312 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
1313 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
1314 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
1316 if (sc->sc_hwrev & URTW_HWREV_8187) {
1318 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
1322 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
1323 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
1324 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
1325 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] =
1330 error = urtw_eprom_read32(sc, 0x1b, &data);
1333 sc->sc_txpwr_cck[11] = data & 0xf;
1334 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4;
1337 error = urtw_eprom_read32(sc, 0xa, &data);
1340 sc->sc_txpwr_cck[12] = data & 0xf;
1341 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4;
1344 error = urtw_eprom_read32(sc, 0x1c, &data);
1347 sc->sc_txpwr_cck[13] = data & 0xf;
1348 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4;
1349 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8;
1350 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12;
1357 urtw_get_macaddr(struct urtw_softc *sc)
1359 struct ieee80211com *ic = &sc->sc_ic;
1363 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
1368 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
1373 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
1383 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
1394 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
1397 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
1400 error = urtw_eprom_ck(sc);
1403 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
1406 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
1425 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
1429 error = urtw_eprom_writebit(sc, 0);
1434 error = urtw_eprom_ck(sc);
1437 error = urtw_eprom_readbit(sc, &data16);
1444 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
1447 error = urtw_eprom_ck(sc);
1452 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
1459 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
1464 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
1473 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
1479 error = urtw_eprom_writebit(sc, buf[i]);
1482 error = urtw_eprom_ck(sc);
1491 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
1496 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1498 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
1500 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
1507 urtw_eprom_ck(struct urtw_softc *sc)
1513 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1514 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
1517 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1518 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
1525 urtw_eprom_cs(struct urtw_softc *sc, int able)
1530 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1532 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
1534 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
1541 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx)
1552 error = usbd_do_request(sc->sc_udev, &req, data);
1557 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
1568 error = usbd_do_request(sc->sc_udev, &req, data);
1573 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx)
1584 error = usbd_do_request(sc->sc_udev, &req, data);
1590 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx)
1601 error = usbd_do_request(sc->sc_udev, &req, data);
1607 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx)
1617 return (usbd_do_request(sc->sc_udev, &req, &data));
1621 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
1631 return (usbd_do_request(sc->sc_udev, &req, &data));
1635 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx)
1646 return (usbd_do_request(sc->sc_udev, &req, &data));
1650 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx)
1661 return (usbd_do_request(sc->sc_udev, &req, &data));
1665 urtw_set_mode(struct urtw_softc *sc, uint32_t mode)
1670 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1673 urtw_write8_m(sc, URTW_EPROM_CMD, data);
1679 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
1684 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1688 urtw_read8_m(sc, URTW_CONFIG3, &data);
1689 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
1690 urtw_write32_m(sc, URTW_ANAPARAM, val);
1691 urtw_read8_m(sc, URTW_CONFIG3, &data);
1692 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
1694 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1702 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
1707 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1711 urtw_read8_m(sc, URTW_CONFIG3, &data);
1712 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
1713 urtw_write32_m(sc, URTW_ANAPARAM2, val);
1714 urtw_read8_m(sc, URTW_CONFIG3, &data);
1715 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
1717 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1725 urtw_intr_disable(struct urtw_softc *sc)
1729 urtw_write16_m(sc, URTW_INTR_MASK, 0);
1735 urtw_reset(struct urtw_softc *sc)
1740 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON);
1743 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON);
1747 error = urtw_intr_disable(sc);
1750 usbd_delay_ms(sc->sc_udev, 100);
1752 error = urtw_write8e(sc, 0x18, 0x10);
1755 error = urtw_write8e(sc, 0x18, 0x11);
1758 error = urtw_write8e(sc, 0x18, 0x00);
1761 usbd_delay_ms(sc->sc_udev, 100);
1763 urtw_read8_m(sc, URTW_CMD, &data);
1765 urtw_write8_m(sc, URTW_CMD, data);
1766 usbd_delay_ms(sc->sc_udev, 100);
1768 urtw_read8_m(sc, URTW_CMD, &data);
1770 printf("%s: reset timeout\n", sc->sc_dev.dv_xname);
1774 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
1777 usbd_delay_ms(sc->sc_udev, 100);
1779 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON);
1782 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON);
1790 urtw_led_on(struct urtw_softc *sc, int type)
1795 switch (sc->sc_gpio_ledpin) {
1797 urtw_write8_m(sc, URTW_GPIO, 0x01);
1798 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
1805 sc->sc_gpio_ledon = 1;
1811 urtw_led_off(struct urtw_softc *sc, int type)
1816 switch (sc->sc_gpio_ledpin) {
1818 urtw_write8_m(sc, URTW_GPIO, 0x01);
1819 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01);
1826 sc->sc_gpio_ledon = 0;
1833 urtw_led_mode0(struct urtw_softc *sc, int mode)
1837 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
1840 if (sc->sc_gpio_ledinprogress == 1)
1843 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
1844 sc->sc_gpio_blinktime = 2;
1847 sc->sc_gpio_ledstate = URTW_LED_ON;
1853 switch (sc->sc_gpio_ledstate) {
1855 if (sc->sc_gpio_ledinprogress != 0)
1857 urtw_led_on(sc, URTW_LED_GPIO);
1860 if (sc->sc_gpio_ledinprogress != 0)
1862 sc->sc_gpio_ledinprogress = 1;
1863 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
1865 if (!usbd_is_dying(sc->sc_udev))
1866 timeout_add_msec(&sc->sc_led_ch, 100);
1869 urtw_led_on(sc, URTW_LED_GPIO);
1870 usbd_delay_ms(sc->sc_udev, 100);
1871 urtw_led_off(sc, URTW_LED_GPIO);
1880 urtw_led_mode1(struct urtw_softc *sc, int mode)
1886 urtw_led_mode2(struct urtw_softc *sc, int mode)
1892 urtw_led_mode3(struct urtw_softc *sc, int mode)
1900 struct urtw_softc *sc = arg;
1902 if (sc->sc_strategy != URTW_SW_LED_MODE0)
1905 urtw_led_blink(sc);
1911 struct urtw_softc *sc = arg;
1917 usb_add_task(sc->sc_udev, &sc->sc_ledtask);
1921 urtw_led_ctl(struct urtw_softc *sc, int mode)
1925 switch (sc->sc_strategy) {
1927 error = urtw_led_mode0(sc, mode);
1930 error = urtw_led_mode1(sc, mode);
1933 error = urtw_led_mode2(sc, mode);
1936 error = urtw_led_mode3(sc, mode);
1946 urtw_led_blink(struct urtw_softc *sc)
1951 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
1952 error = urtw_led_on(sc, URTW_LED_GPIO);
1954 error = urtw_led_off(sc, URTW_LED_GPIO);
1955 sc->sc_gpio_blinktime--;
1956 if (sc->sc_gpio_blinktime == 0)
1959 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
1960 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
1961 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
1965 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
1966 sc->sc_gpio_ledon == 0)
1967 error = urtw_led_on(sc, URTW_LED_GPIO);
1968 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
1969 sc->sc_gpio_ledon == 1)
1970 error = urtw_led_off(sc, URTW_LED_GPIO);
1972 sc->sc_gpio_blinktime = 0;
1973 sc->sc_gpio_ledinprogress = 0;
1977 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
1980 switch (sc->sc_gpio_ledstate) {
1982 if (!usbd_is_dying(sc->sc_udev))
1983 timeout_add_msec(&sc->sc_led_ch, 100);
1992 urtw_update_msr(struct urtw_softc *sc)
1994 struct ieee80211com *ic = &sc->sc_ic;
1998 urtw_read8_m(sc, URTW_MSR, &data);
2002 if (sc->sc_hwrev & URTW_HWREV_8187B)
2005 if (sc->sc_state == IEEE80211_S_RUN) {
2017 urtw_write8_m(sc, URTW_MSR, data);
2049 urtw_set_rate(struct urtw_softc *sc)
2059 urtw_write8_m(sc, URTW_RESP_RATE,
2063 urtw_read16_m(sc, URTW_8187_BRSR, &data);
2069 urtw_write16_m(sc, URTW_8187_BRSR, data);
2075 urtw_intr_enable(struct urtw_softc *sc)
2079 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
2085 urtw_rx_setconf(struct urtw_softc *sc)
2087 struct ifnet *ifp = &sc->sc_ic.ic_if;
2088 struct ieee80211com *ic = &sc->sc_ic;
2092 urtw_read32_m(sc, URTW_RX, &data);
2104 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
2120 urtw_write32_m(sc, URTW_RX, data);
2126 urtw_rx_enable(struct urtw_softc *sc)
2137 rx_data = &sc->sc_rx_data[i];
2139 usbd_setup_xfer(rx_data->xfer, sc->sc_rxpipe, rx_data,
2145 sc->sc_dev.dv_xname);
2150 error = urtw_rx_setconf(sc);
2154 urtw_read8_m(sc, URTW_CMD, &data);
2155 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
2161 urtw_tx_enable(struct urtw_softc *sc)
2167 if (sc->sc_hwrev & URTW_HWREV_8187) {
2168 urtw_read8_m(sc, URTW_CW_CONF, &data8);
2171 urtw_write8_m(sc, URTW_CW_CONF, data8);
2173 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
2177 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
2179 urtw_read32_m(sc, URTW_TX_CONF, &data);
2183 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
2184 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
2189 urtw_write32_m(sc, URTW_TX_CONF, data);
2194 urtw_write32_m(sc, URTW_TX_CONF, data);
2197 urtw_read8_m(sc, URTW_CMD, &data8);
2198 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
2206 struct urtw_softc *sc = ifp->if_softc;
2207 struct urtw_rf *rf = &sc->sc_rf;
2208 struct ieee80211com *ic = &sc->sc_ic;
2213 error = urtw_reset(sc);
2217 urtw_write8_m(sc, 0x85, 0);
2218 urtw_write8_m(sc, URTW_GPIO, 0);
2221 urtw_write8_m(sc, 0x85, 4);
2222 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON);
2226 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2232 error = urtw_set_macaddr(sc, ic->ic_myaddr);
2235 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2239 error = urtw_update_msr(sc);
2243 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0);
2244 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
2245 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81);
2246 error = urtw_set_rate(sc);
2256 urtw_write16_m(sc, 0x5e, 1);
2257 urtw_write16_m(sc, 0xfe, 0x10);
2258 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80);
2259 urtw_write8_m(sc, 0xff, 0x60);
2260 urtw_write16_m(sc, 0x5e, 0);
2261 urtw_write8_m(sc, 0x85, 4);
2263 error = urtw_intr_enable(sc);
2268 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0;
2269 sc->sc_txtimer = 0;
2271 if (!(sc->sc_flags & URTW_INIT_ONCE)) {
2272 error = urtw_open_pipes(sc);
2275 error = urtw_alloc_rx_data_list(sc);
2278 error = urtw_alloc_tx_data_list(sc);
2281 sc->sc_flags |= URTW_INIT_ONCE;
2284 error = urtw_rx_enable(sc);
2287 error = urtw_tx_enable(sc);
2307 urtw_set_multi(struct urtw_softc *sc)
2309 struct arpcom *ac = &sc->sc_ic.ic_ac;
2322 struct urtw_softc *sc = ifp->if_softc;
2323 struct ieee80211com *ic = &sc->sc_ic;
2327 if (usbd_is_dying(sc->sc_udev))
2330 usbd_ref_incr(sc->sc_udev);
2346 ((ifp->if_flags ^ sc->sc_if_flags) &
2348 urtw_set_multi(sc);
2351 sc->sc_init(ifp);
2357 sc->sc_if_flags = ifp->if_flags;
2368 urtw_set_multi(sc);
2382 urtw_set_chan(sc, ic->ic_ibss_chan);
2394 sc->sc_init(ifp);
2400 usbd_ref_decr(sc->sc_udev);
2408 struct urtw_softc *sc = ifp->if_softc;
2409 struct ieee80211com *ic = &sc->sc_ic;
2421 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT ||
2422 sc->sc_tx_normal_queued >= URTW_TX_DATA_LIST_COUNT) {
2434 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL)
2454 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL)
2462 sc->sc_txtimer = 5;
2469 struct urtw_softc *sc = ifp->if_softc;
2473 if (sc->sc_txtimer > 0) {
2474 if (--sc->sc_txtimer == 0) {
2475 printf("%s: device timeout\n", sc->sc_dev.dv_xname);
2490 struct urtw_softc *sc = data->sc;
2491 struct ieee80211com *ic = &sc->sc_ic;
2500 sc->sc_dev.dv_xname, usbd_errstr(status));
2503 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low);
2514 sc->sc_txtimer = 0;
2516 sc->sc_tx_low_queued--;
2528 struct urtw_softc *sc = data->sc;
2529 struct ieee80211com *ic = &sc->sc_ic;
2538 sc->sc_dev.dv_xname, usbd_errstr(status));
2541 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal);
2552 sc->sc_txtimer = 0;
2554 sc->sc_tx_normal_queued--;
2562 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
2565 struct ieee80211com *ic = &sc->sc_ic;
2585 if (sc->sc_drvbpf != NULL) {
2587 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
2595 mb.m_len = sc->sc_txtap_len;
2600 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT);
2604 if (sc->sc_hwrev & URTW_HWREV_8187)
2612 data = &sc->sc_tx_data[sc->sc_txidx];
2613 sc->sc_txidx = (sc->sc_txidx + 1) % URTW_TX_DATA_LIST_COUNT;
2623 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0))
2637 data->buf[3] = sc->sc_currate;
2645 if (sc->sc_hwrev & URTW_HWREV_8187) {
2661 (prior == URTW_PRIORITY_LOW) ? sc->sc_txpipe_low :
2662 sc->sc_txpipe_normal, data, data->buf, xferlen,
2668 sc->sc_dev.dv_xname, usbd_errstr(error));
2672 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
2675 sc->sc_dev.dv_xname, error);
2678 sc->sc_tx_low_queued++;
2680 sc->sc_tx_normal_queued++;
2686 urtw_8225_usb_init(struct urtw_softc *sc)
2691 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2692 urtw_write8_m(sc, URTW_GPIO, 0);
2693 error = urtw_read8e(sc, 0x53, &data);
2696 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2699 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2700 urtw_write8_m(sc, URTW_GPIO, 0x20);
2701 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2703 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2704 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2705 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2707 usbd_delay_ms(sc->sc_udev, 500);
2713 urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2717 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2723 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2729 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24));
2730 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16));
2731 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8));
2732 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff)));
2735 * usbd_delay_ms(sc->sc_udev, 1);
2742 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2745 return (urtw_8187_write_phy(sc, addr, data));
2749 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2752 return (urtw_8187_write_phy(sc, addr, data | 0x10000));
2756 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2760 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2761 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2762 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2763 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2769 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2774 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2775 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2789 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2792 urtw_8187_write_phy_cck(sc, 0x44 + i,
2795 usbd_delay_ms(sc->sc_udev, 1);
2805 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON);
2808 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2809 urtw_8187_write_phy_ofdm(sc, 6, 0);
2810 urtw_8187_write_phy_ofdm(sc, 8, 0);
2812 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2814 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2815 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2816 usbd_delay_ms(sc->sc_udev, 1);
2822 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2826 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2827 usbd_delay_ms(sc->sc_udev, 1);
2835 struct urtw_softc *sc = rf->rf_sc;
2840 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON);
2844 error = urtw_8225_usb_init(sc);
2848 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2849 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */
2850 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff);
2851 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2853 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2856 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2857 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2861 error = urtw_8185_rf_pins_enable(sc);
2865 usbd_delay_ms(sc->sc_udev, 500);
2868 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2871 usbd_delay_ms(sc->sc_udev, 50);
2872 urtw_8225_write(sc, 0x2, 0xc4d);
2873 usbd_delay_ms(sc->sc_udev, 200);
2874 urtw_8225_write(sc, 0x2, 0x44d);
2875 usbd_delay_ms(sc->sc_udev, 200);
2876 urtw_8225_write(sc, 0x0, 0x127);
2879 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1));
2880 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]);
2883 urtw_8225_write(sc, 0x0, 0x27);
2884 urtw_8225_write(sc, 0x0, 0x22f);
2887 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2888 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2892 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2894 usbd_delay_ms(sc->sc_udev, 1);
2897 error = urtw_8225_setgain(sc, 4);
2902 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2904 usbd_delay_ms(sc->sc_udev, 1);
2907 urtw_write8_m(sc, 0x5b, 0x0d);
2909 error = urtw_8225_set_txpwrlvl(sc, 1);
2913 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2914 usbd_delay_ms(sc->sc_udev, 1);
2915 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2916 usbd_delay_ms(sc->sc_udev, 1);
2919 error = urtw_8185_tx_antenna(sc, 0x3);
2922 urtw_write32_m(sc, 0x94, 0x3dc00002);
2932 struct urtw_softc *sc = rf->rf_sc;
2933 struct ieee80211com *ic = &sc->sc_ic;
2937 error = urtw_8225_set_txpwrlvl(sc, chan);
2940 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]);
2941 usbd_delay_ms(sc->sc_udev, 10);
2943 urtw_write8_m(sc, URTW_SIFS, 0x22);
2945 if (sc->sc_state == IEEE80211_S_ASSOC &&
2947 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_DS_SHSLOT);
2949 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_DS_SLOT);
2952 urtw_write8_m(sc, URTW_DIFS, 0x14);
2953 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14);
2954 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
2956 urtw_write8_m(sc, URTW_DIFS, 0x24);
2957 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24);
2958 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
2968 struct urtw_softc *sc = rf->rf_sc;
2975 urtw_8225_write(sc, 0x0c, 0x850);
2977 urtw_8225_write(sc, 0x0c, 0x50);
2980 error = urtw_8225_setgain(sc, rf->sens);
2984 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]);
2993 struct urtw_softc *sc = ifp->if_softc;
2994 struct ieee80211com *ic = &sc->sc_ic;
3003 timeout_del(&sc->scan_to);
3004 timeout_del(&sc->sc_led_ch);
3006 urtw_intr_disable(sc);
3007 urtw_read8_m(sc, URTW_CMD, &data);
3010 urtw_write8_m(sc, URTW_CMD, data);
3012 if (sc->sc_rxpipe != NULL)
3013 usbd_abort_pipe(sc->sc_rxpipe);
3014 if (sc->sc_txpipe_low != NULL)
3015 usbd_abort_pipe(sc->sc_txpipe_low);
3016 if (sc->sc_txpipe_normal != NULL)
3017 usbd_abort_pipe(sc->sc_txpipe_normal);
3036 struct urtw_softc *sc = data->sc;
3037 struct ieee80211com *ic = &sc->sc_ic;
3051 usbd_clear_endpoint_stall_async(sc->sc_rxpipe);
3062 if (sc->sc_hwrev & URTW_HWREV_8187)
3077 if (sc->sc_hwrev & URTW_HWREV_8187) {
3097 sc->sc_dev.dv_xname);
3104 sc->sc_dev.dv_xname);
3120 if (sc->sc_drvbpf != NULL) {
3122 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
3130 mb.m_len = sc->sc_rxtap_len;
3135 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN);
3140 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
3167 usbd_setup_xfer(xfer, sc->sc_rxpipe, data, data->buf, MCLBYTES,
3173 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3180 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3181 usbd_delay_ms(sc->sc_udev, 1);
3182 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3183 usbd_delay_ms(sc->sc_udev, 1);
3184 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3185 usbd_delay_ms(sc->sc_udev, 1);
3186 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3187 usbd_delay_ms(sc->sc_udev, 1);
3193 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3198 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3199 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3204 cck_pwrlvl += sc->sc_txpwr_cck_base;
3210 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3212 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3214 usbd_delay_ms(sc->sc_udev, 1);
3219 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3222 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON);
3226 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3227 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3228 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3229 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3230 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3232 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3234 usbd_delay_ms(sc->sc_udev, 1);
3242 struct urtw_softc *sc = rf->rf_sc;
3248 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON);
3252 error = urtw_8225_usb_init(sc);
3256 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
3257 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */
3258 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff);
3259 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
3261 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3264 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
3265 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3269 error = urtw_8185_rf_pins_enable(sc);
3273 usbd_delay_ms(sc->sc_udev, 1000);
3276 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
3278 usbd_delay_ms(sc->sc_udev, 1);
3280 usbd_delay_ms(sc->sc_udev, 50);
3282 urtw_8225_write(sc, 0x0, 0x1b7);
3285 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1));
3286 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]);
3289 urtw_8225_write(sc, 0x3, 0x2);
3290 urtw_8225_write(sc, 0x5, 0x4);
3291 urtw_8225_write(sc, 0x0, 0xb7);
3292 urtw_8225_write(sc, 0x2, 0xc4d);
3293 usbd_delay_ms(sc->sc_udev, 100);
3294 urtw_8225_write(sc, 0x2, 0x44d);
3295 usbd_delay_ms(sc->sc_udev, 100);
3297 error = urtw_8225_read(sc, 0x6, &data32);
3301 printf("%s: expect 0xe6!! (0x%x)\n", sc->sc_dev.dv_xname,
3304 urtw_8225_write(sc, 0x02, 0x0c4d);
3305 usbd_delay_ms(sc->sc_udev, 200);
3306 urtw_8225_write(sc, 0x02, 0x044d);
3307 usbd_delay_ms(sc->sc_udev, 100);
3308 error = urtw_8225_read(sc, 0x6, &data32);
3313 sc->sc_dev.dv_xname);
3315 usbd_delay_ms(sc->sc_udev, 100);
3317 urtw_8225_write(sc, 0x0, 0x2bf);
3319 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
3320 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
3324 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
3328 error = urtw_8225v2_setgain(sc, 4);
3333 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
3337 urtw_write8_m(sc, 0x5b, 0x0d);
3339 error = urtw_8225v2_set_txpwrlvl(sc, 1);
3343 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
3344 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
3347 error = urtw_8185_tx_antenna(sc, 0x3);
3350 urtw_write32_m(sc, 0x94, 0x3dc00002);
3360 struct urtw_softc *sc = rf->rf_sc;
3361 struct ieee80211com *ic = &sc->sc_ic;
3365 error = urtw_8225v2_set_txpwrlvl(sc, chan);
3369 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]);
3370 usbd_delay_ms(sc->sc_udev, 10);
3372 urtw_write8_m(sc, URTW_SIFS, 0x22);
3374 if(sc->sc_state == IEEE80211_S_ASSOC &&
3376 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_DS_SHSLOT);
3378 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_DS_SLOT);
3381 urtw_write8_m(sc, URTW_DIFS, 0x14);
3382 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14);
3383 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
3385 urtw_write8_m(sc, URTW_DIFS, 0x24);
3386 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24);
3387 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
3395 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c)
3397 struct urtw_rf *rf = &sc->sc_rf;
3398 struct ieee80211com *ic = &sc->sc_ic;
3410 urtw_read32_m(sc, URTW_TX_CONF, &data);
3412 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
3416 sc->sc_dev.dv_xname);
3419 usbd_delay_ms(sc->sc_udev, 10);
3420 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE);
3429 struct urtw_softc *sc = arg;
3430 struct ieee80211com *ic = &sc->sc_ic;
3433 if (usbd_is_dying(sc->sc_udev))
3436 usbd_ref_incr(sc->sc_udev);
3441 usbd_ref_decr(sc->sc_udev);
3447 struct urtw_softc *sc = arg;
3448 struct ieee80211com *ic = &sc->sc_ic;
3453 if (usbd_is_dying(sc->sc_udev))
3458 switch (sc->sc_state) {
3462 (void)urtw_led_off(sc, URTW_LED_GPIO);
3467 urtw_set_chan(sc, ic->ic_bss->ni_chan);
3468 if (!usbd_is_dying(sc->sc_udev))
3469 timeout_add_msec(&sc->scan_to, 200);
3474 urtw_set_chan(sc, ic->ic_bss->ni_chan);
3481 error = urtw_set_bssid(sc, ni->ni_bssid);
3484 urtw_update_msr(sc);
3486 urtw_write16_m(sc, URTW_ATIM_WND, 2);
3487 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
3488 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
3489 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff);
3490 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
3493 sc->sc_dev.dv_xname, error);
3497 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg);
3502 sc->sc_dev.dv_xname));
3506 urtw_8187b_update_wmm(struct urtw_softc *sc)
3508 struct ieee80211com *ic = &sc->sc_ic;
3528 urtw_write32_m(sc, URTW_AC_VO, data);
3529 urtw_write32_m(sc, URTW_AC_VI, data);
3530 urtw_write32_m(sc, URTW_AC_BE, data);
3531 urtw_write32_m(sc, URTW_AC_BK, data);
3538 urtw_8187b_reset(struct urtw_softc *sc)
3543 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3547 urtw_read8_m(sc, URTW_CONFIG3, &data);
3548 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE |
3551 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON);
3552 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON);
3553 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON);
3555 urtw_write8_m(sc, 0x61, 0x10);
3556 urtw_read8_m(sc, 0x62, &data);
3557 urtw_write8_m(sc, 0x62, data & ~(1 << 5));
3558 urtw_write8_m(sc, 0x62, data | (1 << 5));
3560 urtw_read8_m(sc, URTW_CONFIG3, &data);
3561 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3563 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3567 urtw_read8_m(sc, URTW_CMD, &data);
3569 urtw_write8_m(sc, URTW_CMD, data);
3570 usbd_delay_ms(sc->sc_udev, 100);
3572 urtw_read8_m(sc, URTW_CMD, &data);
3574 printf("%s: reset timeout\n", sc->sc_dev.dv_xname);
3585 struct urtw_softc *sc = ifp->if_softc;
3586 struct urtw_rf *rf = &sc->sc_rf;
3587 struct ieee80211com *ic = &sc->sc_ic;
3593 error = urtw_8187b_update_wmm(sc);
3596 error = urtw_8187b_reset(sc);
3601 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3605 error = urtw_set_macaddr(sc, ic->ic_myaddr);
3608 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3612 error = urtw_update_msr(sc);
3620 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE |
3622 error = urtw_intr_enable(sc);
3626 error = urtw_write8e(sc, 0x41, 0xf4);
3629 error = urtw_write8e(sc, 0x40, 0x00);
3632 error = urtw_write8e(sc, 0x42, 0x00);
3635 error = urtw_write8e(sc, 0x42, 0x01);
3638 error = urtw_write8e(sc, 0x40, 0x0f);
3641 error = urtw_write8e(sc, 0x42, 0x00);
3644 error = urtw_write8e(sc, 0x42, 0x01);
3648 urtw_read8_m(sc, 0xdb, &data);
3649 urtw_write8_m(sc, 0xdb, data | (1 << 2));
3650 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3);
3651 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3);
3652 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3);
3653 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3);
3654 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3);
3655 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3);
3656 urtw_write8_m(sc, 0x61, 0);
3657 urtw_write8_idx_m(sc, 0x80, 0x0f, 1);
3658 urtw_write8_idx_m(sc, 0x83, 0x03, 1);
3659 urtw_write8_m(sc, 0xda, 0x10);
3660 urtw_write8_idx_m(sc, 0x4d, 0x08, 2);
3662 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b);
3664 urtw_write16_idx_m(sc, 0xec, 0x0800, 1);
3666 urtw_write8_m(sc, URTW_ACM_CONTROL, 0);
3669 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0;
3670 sc->sc_txtimer = 0;
3672 if (!(sc->sc_flags & URTW_INIT_ONCE)) {
3673 error = urtw_open_pipes(sc);
3676 error = urtw_alloc_rx_data_list(sc);
3679 error = urtw_alloc_tx_data_list(sc);
3682 sc->sc_flags |= URTW_INIT_ONCE;
3685 error = urtw_rx_enable(sc);
3688 error = urtw_tx_enable(sc);
3707 urtw_8225v2_b_config_mac(struct urtw_softc *sc)
3713 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg,
3717 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
3718 urtw_write16_m(sc, URTW_INT_MIG, 0);
3720 urtw_write32_idx_m(sc, 0xf0, 0, 1);
3721 urtw_write32_idx_m(sc, 0xf4, 0, 1);
3722 urtw_write8_idx_m(sc, 0xf8, 0, 1);
3724 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001);
3731 urtw_8225v2_b_init_rfe(struct urtw_softc *sc)
3735 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
3736 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
3737 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
3738 usbd_delay_ms(sc->sc_udev, 100);
3745 urtw_8225v2_b_update_chan(struct urtw_softc *sc)
3747 struct ieee80211com *ic = &sc->sc_ic;
3752 urtw_write8_m(sc, URTW_SIFS, 0x22);
3766 urtw_write8_m(sc, URTW_SLOT, slot);
3768 urtw_write8_m(sc, URTW_AC_VO, aifs);
3769 urtw_write8_m(sc, URTW_AC_VI, aifs);
3770 urtw_write8_m(sc, URTW_AC_BE, aifs);
3771 urtw_write8_m(sc, URTW_AC_BK, aifs);
3773 urtw_write8_m(sc, URTW_DIFS, difs);
3774 urtw_write8_m(sc, URTW_8187B_EIFS, eifs);
3783 struct urtw_softc *sc = rf->rf_sc;
3789 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff);
3790 urtw_read8_m(sc, URTW_CW_CONF, &data);
3791 urtw_write8_m(sc, URTW_CW_CONF, data |
3793 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data);
3794 urtw_write8_m(sc, URTW_TX_AGC_CTL, data |
3799 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */
3800 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data);
3801 urtw_write8_m(sc, URTW_RATE_FALLBACK, data |
3804 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
3805 urtw_write16_m(sc, URTW_ATIM_WND, 2);
3806 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1);
3808 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3811 urtw_read8_m(sc, URTW_CONFIG1, &data);
3812 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80);
3813 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3817 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
3818 urtw_8225v2_b_config_mac(sc);
3819 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2);
3821 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3824 urtw_read8_m(sc, URTW_CONFIG3, &data);
3825 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3826 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3830 urtw_8225v2_b_init_rfe(sc);
3833 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg,
3838 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1));
3839 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]);
3842 urtw_8225_write(sc, 0x03, 0x080);
3843 urtw_8225_write(sc, 0x05, 0x004);
3844 urtw_8225_write(sc, 0x00, 0x0b7);
3845 urtw_8225_write(sc, 0x02, 0xc4d);
3846 urtw_8225_write(sc, 0x02, 0x44d);
3847 urtw_8225_write(sc, 0x00, 0x2bf);
3849 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3850 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3851 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3853 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3855 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]);
3856 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80);
3857 urtw_8187_write_phy_ofdm(sc, 0x0e, 0);
3859 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3862 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]);
3864 urtw_8225v2_b_update_chan(sc);
3866 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3867 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3868 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3869 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3879 struct urtw_softc *sc = rf->rf_sc;
3882 error = urtw_8225v2_b_set_txpwrlvl(sc, chan);
3886 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]);
3889 * usbd_delay_ms(sc->sc_udev, 10);
3892 urtw_write16_m(sc, URTW_AC_VO, 0x5114);
3893 urtw_write16_m(sc, URTW_AC_VI, 0x5114);
3894 urtw_write16_m(sc, URTW_AC_BE, 0x5114);
3895 urtw_write16_m(sc, URTW_AC_BK, 0x5114);
3902 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3908 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3909 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3912 if (sc->sc_hwrev & URTW_HWREV_8187B_B) {
3928 cck_pwrlvl += sc->sc_txpwr_cck_base;
3935 if (sc->sc_hwrev & URTW_HWREV_8187B_B) {
3954 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3957 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3961 * usbd_delay_ms(sc->sc_udev, 1);
3968 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3972 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3975 if (sc->sc_hwrev & URTW_HWREV_8187B_B) {
3977 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3978 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3980 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3981 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3985 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3986 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3988 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3989 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3991 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3992 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3998 * usbd_delay_ms(sc->sc_udev, 1);
4005 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid)
4009 urtw_write32_m(sc, URTW_BSSID,
4011 urtw_write16_m(sc, URTW_BSSID + 4,
4021 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr)
4025 urtw_write32_m(sc, URTW_MAC0,
4027 urtw_write16_m(sc, URTW_MAC4,