Lines Matching defs:data
96 #define urtw_read8_m(sc, val, data) do { \
97 error = urtw_read8_c(sc, val, data, 0); \
101 #define urtw_read8_idx_m(sc, val, data, idx) do { \
102 error = urtw_read8_c(sc, val, data, idx); \
106 #define urtw_write8_m(sc, val, data) do { \
107 error = urtw_write8_c(sc, val, data, 0); \
111 #define urtw_write8_idx_m(sc, val, data, idx) do { \
112 error = urtw_write8_c(sc, val, data, idx); \
116 #define urtw_read16_m(sc, val, data) do { \
117 error = urtw_read16_c(sc, val, data, 0); \
121 #define urtw_read16_idx_m(sc, val, data, idx) do { \
122 error = urtw_read16_c(sc, val, data, idx); \
126 #define urtw_write16_m(sc, val, data) do { \
127 error = urtw_write16_c(sc, val, data, 0); \
131 #define urtw_write16_idx_m(sc, val, data, idx) do { \
132 error = urtw_write16_c(sc, val, data, idx); \
136 #define urtw_read32_m(sc, val, data) do { \
137 error = urtw_read32_c(sc, val, data, 0); \
141 #define urtw_read32_idx_m(sc, val, data, idx) do { \
142 error = urtw_read32_c(sc, val, data, idx); \
146 #define urtw_write32_m(sc, val, data) do { \
147 error = urtw_write32_c(sc, val, data, 0); \
151 #define urtw_write32_idx_m(sc, val, data, idx) do { \
152 error = urtw_write32_c(sc, val, data, idx); \
156 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \
157 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
161 #define urtw_8187_write_phy_cck(sc, val, data) do { \
162 error = urtw_8187_write_phy_cck_c(sc, val, data); \
166 #define urtw_8225_write(sc, val, data) do { \
167 error = urtw_8225_write_c(sc, val, data); \
598 uint32_t data;
608 urtw_read32_m(sc, URTW_TX_CONF, &data);
609 data &= URTW_TX_HWREV_MASK;
610 switch (data) {
625 printf("RTL8187 rev 0x%02x", data >> 25);
651 urtw_read32_m(sc, URTW_RX, &data);
652 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
866 struct urtw_rx_data *data = &sc->sc_rx_data[i];
868 data->sc = sc;
870 data->xfer = usbd_alloc_xfer(sc->sc_udev);
871 if (data->xfer == NULL) {
878 if (usbd_alloc_buffer(data->xfer, URTW_RX_MAXSIZE) == NULL) {
885 MGETHDR(data->m, M_DONTWAIT, MT_DATA);
886 if (data->m == NULL) {
892 MCLGET(data->m, M_DONTWAIT);
893 if (!(data->m->m_flags & M_EXT)) {
899 data->buf = mtod(data->m, uint8_t *);
919 struct urtw_rx_data *data = &sc->sc_rx_data[i];
921 if (data->xfer != NULL) {
922 usbd_free_xfer(data->xfer);
923 data->xfer = NULL;
925 if (data->m != NULL) {
926 m_freem(data->m);
927 data->m = NULL;
938 struct urtw_tx_data *data = &sc->sc_tx_data[i];
940 data->sc = sc;
941 data->ni = NULL;
943 data->xfer = usbd_alloc_xfer(sc->sc_udev);
944 if (data->xfer == NULL) {
951 data->buf = usbd_alloc_buffer(data->xfer, URTW_TX_MAXSIZE);
952 if (data->buf == NULL) {
959 if (((unsigned long)data->buf) % 4)
961 sc->sc_dev.dv_xname, data->buf);
984 struct urtw_tx_data *data = &sc->sc_tx_data[i];
986 if (data->xfer != NULL) {
987 usbd_free_xfer(data->xfer);
988 data->xfer = NULL;
990 if (data->ni != NULL) {
991 ieee80211_release_node(ic, data->ni);
992 data->ni = NULL;
1065 uint16_t data)
1075 data = htole16(data);
1076 return (usbd_do_request(sc->sc_udev, &req, &data));
1080 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
1163 if (data != NULL)
1164 *data = value;
1170 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
1189 error = urtw_8225_write_s16(sc, addr, 0x8225, data);
1205 uint32_t data;
1217 error = urtw_8225_read(sc, 0x8, &data);
1220 if (data != 0x588)
1223 error = urtw_8225_read(sc, 0x9, &data);
1226 if (data != 0x700)
1240 uint32_t data;
1246 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
1249 switch (data & 0xff) {
1281 printf("unsupported RF chip %d", data & 0xff);
1289 uint32_t data;
1292 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
1295 sc->sc_txpwr_cck_base = data & 0xf;
1296 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
1299 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
1302 sc->sc_txpwr_cck[i] = data & 0xf;
1303 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
1304 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
1305 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
1308 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
1311 sc->sc_txpwr_cck[i + 6] = data & 0xf;
1312 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
1313 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
1314 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
1319 &data);
1322 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
1323 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
1324 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
1326 (data & 0xf000) >> 12;
1330 error = urtw_eprom_read32(sc, 0x1b, &data);
1333 sc->sc_txpwr_cck[11] = data & 0xf;
1334 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4;
1337 error = urtw_eprom_read32(sc, 0xa, &data);
1340 sc->sc_txpwr_cck[12] = data & 0xf;
1341 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4;
1344 error = urtw_eprom_read32(sc, 0x1c, &data);
1347 sc->sc_txpwr_cck[13] = data & 0xf;
1348 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4;
1349 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8;
1350 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12;
1361 uint32_t data;
1363 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
1366 ic->ic_myaddr[0] = data & 0xff;
1367 ic->ic_myaddr[1] = (data & 0xff00) >> 8;
1368 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
1371 ic->ic_myaddr[2] = data & 0xff;
1372 ic->ic_myaddr[3] = (data & 0xff00) >> 8;
1373 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
1376 ic->ic_myaddr[4] = data & 0xff;
1377 ic->ic_myaddr[5] = (data & 0xff00) >> 8;
1383 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
1391 *data = 0;
1441 (*data) |= (data16 << (15 - i));
1459 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
1465 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
1493 uint8_t data;
1496 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1498 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
1500 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
1509 uint8_t data;
1513 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1514 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
1517 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1518 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
1527 uint8_t data;
1530 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1532 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
1534 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
1541 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx)
1552 error = usbd_do_request(sc->sc_udev, &req, data);
1557 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
1568 error = usbd_do_request(sc->sc_udev, &req, data);
1573 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx)
1584 error = usbd_do_request(sc->sc_udev, &req, data);
1585 *data = letoh16(*data);
1590 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx)
1601 error = usbd_do_request(sc->sc_udev, &req, data);
1602 *data = letoh32(*data);
1607 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx)
1617 return (usbd_do_request(sc->sc_udev, &req, &data));
1621 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
1631 return (usbd_do_request(sc->sc_udev, &req, &data));
1635 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx)
1645 data = htole16(data);
1646 return (usbd_do_request(sc->sc_udev, &req, &data));
1650 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx)
1660 data = htole32(data);
1661 return (usbd_do_request(sc->sc_udev, &req, &data));
1667 uint8_t data;
1670 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1671 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT);
1672 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK);
1673 urtw_write8_m(sc, URTW_EPROM_CMD, data);
1681 uint8_t data;
1688 urtw_read8_m(sc, URTW_CONFIG3, &data);
1689 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
1691 urtw_read8_m(sc, URTW_CONFIG3, &data);
1692 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
1704 uint8_t data;
1711 urtw_read8_m(sc, URTW_CONFIG3, &data);
1712 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
1714 urtw_read8_m(sc, URTW_CONFIG3, &data);
1715 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
1737 uint8_t data;
1763 urtw_read8_m(sc, URTW_CMD, &data);
1764 data = (data & 2) | URTW_CMD_RST;
1765 urtw_write8_m(sc, URTW_CMD, data);
1768 urtw_read8_m(sc, URTW_CMD, &data);
1769 if (data & URTW_CMD_RST) {
1995 uint8_t data;
1998 urtw_read8_m(sc, URTW_MSR, &data);
1999 data &= ~URTW_MSR_LINK_MASK;
2003 data |= URTW_MSR_LINK_ENEDCA;
2009 data |= URTW_MSR_LINK_STA;
2015 data |= URTW_MSR_LINK_NONE;
2017 urtw_write8_m(sc, URTW_MSR, data);
2052 uint16_t data;
2063 urtw_read16_m(sc, URTW_8187_BRSR, &data);
2064 data &= ~URTW_BRSR_MBR_8185;
2067 data |= (1 << i);
2069 urtw_write16_m(sc, URTW_8187_BRSR, data);
2089 uint32_t data;
2092 urtw_read32_m(sc, URTW_RX, &data);
2093 data = data &~ URTW_RX_FILTER_MASK;
2095 data = data | URTW_RX_FILTER_CTL;
2097 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
2098 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
2101 data = data | URTW_RX_FILTER_ICVERR;
2102 data = data | URTW_RX_FILTER_PWR;
2105 data = data | URTW_RX_FILTER_CRCERR;
2109 data = data | URTW_RX_FILTER_ALLMAC;
2111 data = data | URTW_RX_FILTER_NICMAC;
2112 data = data | URTW_RX_CHECK_BSSID;
2115 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
2116 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY;
2117 data = data &~ URTW_MAX_RX_DMA_MASK;
2118 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
2120 urtw_write32_m(sc, URTW_RX, data);
2130 uint8_t data;
2154 urtw_read8_m(sc, URTW_CMD, &data);
2155 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
2164 uint32_t data;
2179 urtw_read32_m(sc, URTW_TX_CONF, &data);
2180 data &= ~URTW_TX_LOOPBACK_MASK;
2181 data |= URTW_TX_LOOPBACK_NONE;
2182 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
2183 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
2184 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
2185 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
2186 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
2187 data &= ~URTW_TX_SWPLCPLEN;
2188 data |= URTW_TX_NOICV;
2189 urtw_write32_m(sc, URTW_TX_CONF, data);
2191 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE |
2194 urtw_write32_m(sc, URTW_TX_CONF, data);
2320 urtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2362 ifr = (struct ifreq *)data;
2379 error = ieee80211_ioctl(ifp, cmd, data);
2388 error = ieee80211_ioctl(ifp, cmd, data);
2489 struct urtw_tx_data *data = priv;
2490 struct urtw_softc *sc = data->sc;
2511 ieee80211_release_node(ic, data->ni);
2512 data->ni = NULL;
2527 struct urtw_tx_data *data = priv;
2528 struct urtw_softc *sc = data->sc;
2549 ieee80211_release_node(ic, data->ni);
2550 data->ni = NULL;
2566 struct urtw_tx_data *data;
2612 data = &sc->sc_tx_data[sc->sc_txidx];
2615 bzero(data->buf, URTW_TX_MAXSIZE);
2616 data->buf[0] = m0->m_pkthdr.len & 0xff;
2617 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8;
2618 data->buf[1] |= (1 << 7);
2624 data->buf[2] |= 1;
2629 data->buf[2] |= (1 << 1);
2631 data->buf[2] |= (urtw_rate2rtl(2) << 3);
2637 data->buf[3] = sc->sc_currate;
2640 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]);
2642 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate);
2646 data->buf[8] = 3; /* CW minimum */
2647 data->buf[8] |= (7 << 4); /* CW maximum */
2648 data->buf[9] |= 11; /* retry limitation */
2649 m_copydata(m0, 0, m0->m_pkthdr.len, &data->buf[12]);
2651 data->buf[21] |= 11; /* retry limitation */
2652 m_copydata(m0, 0, m0->m_pkthdr.len, &data->buf[32]);
2655 data->ni = ni;
2660 usbd_setup_xfer(data->xfer,
2662 sc->sc_txpipe_normal, data, data->buf, xferlen,
2665 error = usbd_transfer(data->xfer);
2688 uint8_t data;
2693 error = urtw_read8e(sc, 0x53, &data);
2696 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2723 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2728 phyw = ((data << 8) | (addr | 0x80));
2742 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2744 data = data & 0xff;
2745 return (urtw_8187_write_phy(sc, addr, data));
2749 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2751 data = data & 0xff;
2752 return (urtw_8187_write_phy(sc, addr, data | 0x10000));
2837 uint16_t data;
2849 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */
2995 uint8_t data;
3007 urtw_read8_m(sc, URTW_CMD, &data);
3008 data &= ~URTW_CMD_TX_ENABLE;
3009 data &= ~URTW_CMD_RX_ENABLE;
3010 urtw_write8_m(sc, URTW_CMD, data);
3035 struct urtw_rx_data *data = priv;
3036 struct urtw_softc *sc = data->sc;
3069 desc = data->buf + len;
3110 m = data->m;
3111 data->m = mnew;
3112 data->buf = mtod(mnew, uint8_t *);
3167 usbd_setup_xfer(xfer, sc->sc_rxpipe, data, data->buf, MCLBYTES,
3244 uint16_t data;
3257 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */
3400 uint32_t data;
3410 urtw_read32_m(sc, URTW_TX_CONF, &data);
3411 data &= ~URTW_TX_LOOPBACK_MASK;
3412 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
3420 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE);
3510 uint32_t data;
3524 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */
3528 urtw_write32_m(sc, URTW_AC_VO, data);
3529 urtw_write32_m(sc, URTW_AC_VI, data);
3530 urtw_write32_m(sc, URTW_AC_BE, data);
3531 urtw_write32_m(sc, URTW_AC_BK, data);
3540 uint8_t data;
3547 urtw_read8_m(sc, URTW_CONFIG3, &data);
3548 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE |
3556 urtw_read8_m(sc, 0x62, &data);
3557 urtw_write8_m(sc, 0x62, data & ~(1 << 5));
3558 urtw_write8_m(sc, 0x62, data | (1 << 5));
3560 urtw_read8_m(sc, URTW_CONFIG3, &data);
3561 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3567 urtw_read8_m(sc, URTW_CMD, &data);
3568 data = (data & 2) | URTW_CMD_RST;
3569 urtw_write8_m(sc, URTW_CMD, data);
3572 urtw_read8_m(sc, URTW_CMD, &data);
3573 if (data & URTW_CMD_RST) {
3588 uint8_t data;
3648 urtw_read8_m(sc, 0xdb, &data);
3649 urtw_write8_m(sc, 0xdb, data | (1 << 2));
3785 uint8_t data;
3790 urtw_read8_m(sc, URTW_CW_CONF, &data);
3791 urtw_write8_m(sc, URTW_CW_CONF, data |
3793 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data);
3794 urtw_write8_m(sc, URTW_TX_AGC_CTL, data |
3800 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data);
3801 urtw_write8_m(sc, URTW_RATE_FALLBACK, data |
3811 urtw_read8_m(sc, URTW_CONFIG1, &data);
3812 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80);
3824 urtw_read8_m(sc, URTW_CONFIG3, &data);
3825 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);