Lines Matching defs:dc
83 pcitag_t tag, struct tga_devconfig *dc);
84 unsigned tga_getdotclock(struct tga_devconfig *dc);
200 tga_getdevconfig(memt, pc, tag, dc)
204 struct tga_devconfig *dc;
212 dc->dc_memt = memt;
214 dc->dc_pcitag = tag;
220 &dc->dc_pcipaddr, &pcisize, NULL))
224 if (bus_space_map(memt, dc->dc_pcipaddr, pcisize,
225 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh))
228 dc->dc_vaddr = dc->dc_memh;
230 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh);
235 dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */
238 bus_space_subregion(dc->dc_memt, dc->dc_memh,
240 &dc->dc_regs);
243 dc->dc_tga_type = tga_identify(dc);
246 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type);
257 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) {
262 dc->dc_tga2 = 0;
267 dc->dc_tga2 = 1;
273 if (dc->dc_tga2) {
274 tga2_init(dc);
277 i = TGARREG(dc, TGA_REG_VHCR) & 0x1ff;
281 dc->dc_wid = 8192;
285 dc->dc_wid = 8196;
289 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */
293 DPRINTF("tga_getdevconfig: dc->dc_wid = %d\n", dc->dc_wid);
299 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */
300 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */
301 TGAWREG(dc, TGA_REG_VHCR,
302 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001));
303 dc->dc_wid -= 4;
306 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8);
307 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */
310 dc->dc_rowbytes, dc->dc_tgaconf->tgac_phys_depth,
311 dc->dc_wid, dc->dc_ht);
315 TGAWREG(dc, TGA_REG_CCBR, 0);
316 TGAWREG(dc, TGA_REG_VVBR, 1);
317 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] +
319 dc->dc_blanked = 1;
320 tga_unblank(dc);
326 dc->dc_videobase, dc->dc_vaddr, tgac->tgac_dbuf[0],
335 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);
339 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t))
340 *(u_int32_t *)(dc->dc_videobase + i) = 0;
344 rip = &dc->dc_rinfo;
347 rip->ri_bits = (void *)dc->dc_videobase;
348 rip->ri_width = dc->dc_wid;
349 rip->ri_height = dc->dc_ht;
350 rip->ri_stride = dc->dc_rowbytes;
351 rip->ri_hw = dc;
403 dc->dc_intrenabled = 0;
568 struct tga_devconfig *dc = sc->sc_dc;
569 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
570 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
582 TGAWREG(dc, TGA_REG_VVBR, 0);
586 TGAWREG(dc, TGA_REG_VVBR, 1);
649 struct tga_devconfig *dc = v;
651 if (dc->dc_intrenabled) {
653 dc->dc_ramdac_intr = f;
654 TGAWREG(dc, TGA_REG_SISR, 0x00010000);
657 TGAWREG(dc, TGA_REG_SISR, 0x00010001);
658 TGAREGWB(dc, TGA_REG_SISR, 1);
659 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0)
661 f(dc->dc_ramdac_cookie);
662 TGAWREG(dc, TGA_REG_SISR, 0x00000001);
663 TGAREGWB(dc, TGA_REG_SISR, 1);
673 struct tga_devconfig *dc = v;
674 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie;
678 reg = TGARREG(dc, TGA_REG_SISR);
683 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f));
684 TGAREGWB(dc, TGA_REG_SISR, 1);
695 if (dc->dc_ramdac_intr) {
696 dc->dc_ramdac_intr(dcrc);
697 dc->dc_ramdac_intr = NULL;
699 TGAWREG(dc, TGA_REG_SISR, 0x00000001);
700 TGAREGWB(dc, TGA_REG_SISR, 1);
711 struct tga_devconfig *dc = sc->sc_dc;
713 if (offset >= dc->dc_tgaconf->tgac_cspace_size || offset < 0)
720 offset += dc->dc_tgaconf->tgac_cspace_size / 2;
782 struct tga_devconfig *dc = sc->sc_dc;
783 struct rasops_info *ri = &dc->dc_rinfo;
828 struct tga_devconfig *dc = sc->sc_dc;
829 struct rasops_info *ri = &dc->dc_rinfo;
899 tga_blank(dc)
900 struct tga_devconfig *dc;
903 if (!dc->dc_blanked) {
904 dc->dc_blanked = 1;
906 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK);
911 tga_unblank(dc)
912 struct tga_devconfig *dc;
915 if (dc->dc_blanked) {
916 dc->dc_blanked = 0;
918 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK);
926 tga_builtin_set_cursor(dc, cursorp)
927 struct tga_devconfig *dc;
930 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
931 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
953 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04);
956 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04);
959 TGAWREG(dc, TGA_REG_CXYR,
969 TGAWREG(dc, TGA_REG_CCBR,
970 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10));
971 if ((error = copyin(cursorp->image,(char *)(dc->dc_vaddr +
972 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), count)) != 0)
979 tga_builtin_get_cursor(dc, cursorp)
980 struct tga_devconfig *dc;
983 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
984 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
990 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0;
991 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;
992 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;
994 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f;
998 error = copyout((char *)(dc->dc_vaddr +
999 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)),
1010 tga_builtin_set_curpos(dc, curposp)
1011 struct tga_devconfig *dc;
1015 TGAWREG(dc, TGA_REG_CXYR,
1021 tga_builtin_get_curpos(dc, curposp)
1022 struct tga_devconfig *dc;
1026 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;
1027 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;
1032 tga_builtin_get_curmax(dc, curposp)
1033 struct tga_devconfig *dc;
1148 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw;
1154 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units;
1201 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */
1202 TGAWALREG(dc, TGA_REG_GOPR, 3, 0x0003); /* SRC */
1226 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
1227 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
1228 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64);
1229 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64);
1230 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64);
1231 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64);
1232 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64);
1233 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64);
1239 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
1240 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
1245 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
1246 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
1273 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64);
1274 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64);
1275 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64);
1276 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64);
1277 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64);
1278 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64);
1279 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64);
1280 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64);
1288 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
1289 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
1294 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
1295 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
1319 struct tga_devconfig *dc = ri->ri_hw;
1339 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[fg]);
1340 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[bg]);
1344 TGAWREG(dc, TGA_REG_GOPR, 0x3);
1346 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
1349 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1);
1352 TGAWREG(dc, TGA_REG_GMOR, 0x1);
1356 TGAREGWB(dc, TGA_REG_GMOR, 1);
1373 TGAWREG(dc, TGA_REG_GMOR, 0);
1374 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);
1386 struct tga_devconfig *dc = ri->ri_hw;
1398 TGAWREG(dc, TGA_REG_GBCR0, color);
1399 TGAWREG(dc, TGA_REG_GBCR1, color);
1401 TGAWREG(dc, TGA_REG_GBCR2, color);
1402 TGAWREG(dc, TGA_REG_GBCR3, color);
1403 TGAWREG(dc, TGA_REG_GBCR4, color);
1404 TGAWREG(dc, TGA_REG_GBCR5, color);
1405 TGAWREG(dc, TGA_REG_GBCR6, color);
1406 TGAWREG(dc, TGA_REG_GBCR7, color);
1411 TGAWREG(dc, TGA_REG_GOPR, 0x3);
1413 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
1416 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);
1419 TGAWREG(dc, TGA_REG_GMOR, 0x2d);
1423 TGAREGWB(dc, TGA_REG_GMOR, 1);
1431 TGAWREG(dc, TGA_REG_GMOR, 0);
1443 struct tga_devconfig *dc = ri->ri_hw;
1455 TGAWREG(dc, TGA_REG_GBCR0, color);
1456 TGAWREG(dc, TGA_REG_GBCR1, color);
1458 TGAWREG(dc, TGA_REG_GBCR2, color);
1459 TGAWREG(dc, TGA_REG_GBCR3, color);
1460 TGAWREG(dc, TGA_REG_GBCR4, color);
1461 TGAWREG(dc, TGA_REG_GBCR5, color);
1462 TGAWREG(dc, TGA_REG_GBCR6, color);
1463 TGAWREG(dc, TGA_REG_GBCR7, color);
1468 TGAWREG(dc, TGA_REG_GOPR, 0x3);
1470 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
1473 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);
1476 TGAWREG(dc, TGA_REG_GMOR, 0x2d);
1480 TGAREGWB(dc, TGA_REG_GMOR, 1);
1488 TGAWREG(dc, TGA_REG_GMOR, 0);
1500 struct tga_devconfig *dc = v;
1505 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */
1506 TGAREGWB(dc, TGA_REG_EPDR, 1);
1515 struct tga_devconfig *dc = v;
1521 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +
1523 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff);
1524 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE);
1532 struct tga_devconfig *dc = v;
1540 TGAREGWB(dc, TGA_REG_EPSR, 1);
1541 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
1542 TGAREGWB(dc, TGA_REG_EPSR, 1);
1543 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0);
1545 TGAREGRB(dc, TGA_REG_EPSR, 1);
1547 rdval = TGARREG(dc, TGA_REG_EPDR);
1548 TGAREGWB(dc, TGA_REG_EPSR, 1);
1549 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
1560 struct tga_devconfig *dc = v;
1572 TGAREGWB(dc, TGA_REG_EPDR, 1);
1573 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
1574 TGAREGWB(dc, TGA_REG_EPDR, 1);
1575 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val);
1576 TGAREGWB(dc, TGA_REG_EPDR, 1);
1577 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
1586 struct tga_devconfig *dc = v;
1592 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */
1593 TGAREGWB(dc, TGA_REG_EPSR, 1);
1595 rdval = TGARREG(dc, TGA_REG_EPDR);
1604 struct tga_devconfig *dc = v;
1611 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +
1613 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff;
1614 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ);
1620 struct tga_devconfig *dc,
1624 struct monitor *tga_getmonitor(struct tga_devconfig *dc);
1627 tga2_init(dc)
1628 struct tga_devconfig *dc;
1630 struct monitor *m = tga_getmonitor(dc);
1635 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) {
1639 tga2_ics9110_wr(dc, 14300000);
1645 tga2_ics9110_wr(dc, m->dotclock);
1648 TGAWREG(dc, TGA_REG_VHCR,
1654 TGAWREG(dc, TGA_REG_VHCR,
1660 TGAWREG(dc, TGA_REG_VVCR,
1665 TGAWREG(dc, TGA_REG_VVBR, 1);
1666 TGAREGRWB(dc, TGA_REG_VHCR, 3);
1667 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1);
1668 TGAREGRWB(dc, TGA_REG_VVVR, 1);
1669 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff);
1670 TGAREGRWB(dc, TGA_REG_GPMR, 1);
1674 tga2_ics9110_wr(dc, dotclock)
1675 struct tga_devconfig *dc;
1727 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
1737 bus_space_write_4(dc->dc_memt, clock, 0, writeval);
1738 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE);
1740 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
1743 bus_space_write_4(dc->dc_memt, clock, 0, 0x0);
1744 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE);
1748 tga_getmonitor(dc)
1749 struct tga_devconfig *dc;
1751 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f];
1755 tga_getdotclock(dc)
1756 struct tga_devconfig *dc;
1758 return tga_getmonitor(dc)->dotclock;