Lines Matching defs:reg_val
1966 uint32_t reg_val;
1970 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1974 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1975 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1980 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1984 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1988 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1994 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1999 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2000 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2001 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2002 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2003 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2007 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2446 uint16_t reg_slice, reg_val;
2469 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
2471 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
2473 reg_val);
2489 uint32_t reg_val;
2494 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2498 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2499 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2500 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2501 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2506 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
2509 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2518 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2639 uint32_t reg_val;
2644 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2647 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
2650 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2657 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2660 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2661 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2662 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2665 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2670 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2673 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
2674 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
2675 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
2678 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2685 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2688 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
2689 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
2690 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
2691 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
2694 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2710 uint32_t reg_val;
2719 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2723 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2724 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2729 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2732 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2741 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2868 uint32_t reg_val;
2873 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2876 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2877 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2878 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
2881 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2888 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2891 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;
2892 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;
2895 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2902 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2905 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;
2908 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2915 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2918 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;
2921 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
3682 uint32_t pause, asm_dir, reg_val;
3736 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
3739 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3742 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3744 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3747 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);