Lines Matching defs:hw
22 * @hw: pointer to the HW structure
25 igc_init_nvm_params_i225(struct igc_hw *hw)
27 struct igc_nvm_info *nvm = &hw->nvm;
28 uint32_t eecd = IGC_READ_REG(hw, IGC_EECD);
60 if (igc_get_flash_presence_i225(hw)) {
61 hw->nvm.type = igc_nvm_flash_hw;
67 hw->nvm.type = igc_nvm_invm;
78 * @hw: pointer to the HW structure
81 igc_init_mac_params_i225(struct igc_hw *hw)
83 struct igc_mac_info *mac = &hw->mac;
84 struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225;
89 igc_init_mac_ops_generic(hw);
92 hw->phy.media_type = igc_media_type_copper;
100 /* hw initialization */
130 * @hw: pointer to the HW structure
133 igc_init_phy_params_i225(struct igc_hw *hw)
135 struct igc_phy_info *phy = &hw->phy;
140 if (hw->phy.media_type != igc_media_type_copper) {
161 ret_val = hw->phy.ops.reset(hw);
165 ret_val = igc_get_phy_id(hw);
174 * @hw: pointer to the HW structure
179 igc_reset_hw_i225(struct igc_hw *hw)
190 ret_val = igc_disable_pcie_master_generic(hw);
195 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
197 IGC_WRITE_REG(hw, IGC_RCTL, 0);
198 IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP);
199 IGC_WRITE_FLUSH(hw);
203 ctrl = IGC_READ_REG(hw, IGC_CTRL);
206 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST);
208 ret_val = igc_get_auto_rd_done_generic(hw);
219 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
220 IGC_READ_REG(hw, IGC_ICR);
223 ret_val = igc_check_alt_mac_addr_generic(hw);
229 * @hw: pointer to the HW structure
237 igc_acquire_nvm_i225(struct igc_hw *hw)
243 ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
249 * @hw: pointer to the HW structure
255 igc_release_nvm_i225(struct igc_hw *hw)
259 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
263 * @hw: pointer to the HW structure
270 igc_acquire_swfw_sync_i225(struct igc_hw *hw, uint16_t mask)
281 if (igc_get_hw_semaphore_i225(hw)) {
286 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);
293 igc_put_hw_semaphore_generic(hw);
305 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);
307 igc_put_hw_semaphore_generic(hw);
314 * @hw: pointer to the HW structure
321 igc_release_swfw_sync_i225(struct igc_hw *hw, uint16_t mask)
327 while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS)
330 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);
332 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);
334 igc_put_hw_semaphore_generic(hw);
339 * @hw: pointer to the HW structure
346 igc_setup_copper_link_i225(struct igc_hw *hw)
353 ctrl = IGC_READ_REG(hw, IGC_CTRL);
356 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
358 phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM);
360 IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg);
362 ret_val = igc_setup_copper_link_generic(hw);
368 * @hw: pointer to the HW structure
373 igc_get_hw_semaphore_i225(struct igc_hw *hw)
376 int timeout = hw->nvm.word_size + 1;
383 swsm = IGC_READ_REG(hw, IGC_SWSM);
395 if (hw->dev_spec._i225.clear_semaphore_once) {
396 hw->dev_spec._i225.clear_semaphore_once = false;
397 igc_put_hw_semaphore_generic(hw);
399 swsm = IGC_READ_REG(hw, IGC_SWSM);
417 swsm = IGC_READ_REG(hw, IGC_SWSM);
418 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);
421 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)
429 igc_put_hw_semaphore_generic(hw);
438 * @hw: pointer to the HW structure
447 igc_read_nvm_srrd_i225(struct igc_hw *hw, uint16_t offset, uint16_t words,
462 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
463 status = igc_read_nvm_eerd(hw, offset, count, data + i);
464 hw->nvm.ops.release(hw);
477 * @hw: pointer to the HW structure
492 igc_write_nvm_srwr_i225(struct igc_hw *hw, uint16_t offset, uint16_t words,
507 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
508 status = __igc_write_nvm_srwr(hw, offset, count,
510 hw->nvm.ops.release(hw);
522 * @hw: pointer to the HW structure
533 __igc_write_nvm_srwr(struct igc_hw *hw, uint16_t offset, uint16_t words,
536 struct igc_nvm_info *nvm = &hw->nvm;
557 IGC_WRITE_REG(hw, IGC_SRWR, eewr);
560 if (IGC_NVM_RW_REG_DONE & IGC_READ_REG(hw, IGC_SRWR)) {
578 * @hw: pointer to the HW structure
584 igc_validate_nvm_checksum_i225(struct igc_hw *hw)
591 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
596 read_op_ptr = hw->nvm.ops.read;
597 hw->nvm.ops.read = igc_read_nvm_eerd;
599 status = igc_validate_nvm_checksum_generic(hw);
602 hw->nvm.ops.read = read_op_ptr;
604 hw->nvm.ops.release(hw);
613 * @hw: pointer to the HW structure
620 igc_update_nvm_checksum_i225(struct igc_hw *hw)
632 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data);
638 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
639 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
645 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data);
647 hw->nvm.ops.release(hw);
655 ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
658 hw->nvm.ops.release(hw);
663 hw->nvm.ops.release(hw);
665 ret_val = igc_update_flash_i225(hw);
674 * @hw: pointer to the HW structure
677 igc_get_flash_presence_i225(struct igc_hw *hw)
684 eec = IGC_READ_REG(hw, IGC_EECD);
695 * @hw: pointer to the HW structure
699 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, uint32_t burst_counter)
708 IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter);
720 * @hw: pointer to the HW structure
725 igc_write_erase_flash_command_i225(struct igc_hw *hw, uint32_t opcode,
734 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
740 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
751 IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl);
754 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
769 * @hw: pointer to the HW structure
772 igc_update_flash_i225(struct igc_hw *hw)
783 block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) &
786 fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) & IGC_FWSM_FW_VALID_I225;
788 ret_val = igc_pool_flash_update_done_i225(hw);
794 flup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225;
795 IGC_WRITE_REG(hw, IGC_EECD, flup);
797 ret_val = igc_pool_flash_update_done_i225(hw);
809 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225)
813 ret_val = igc_write_erase_flash_command_i225(hw,
825 ret_val = igc_set_flsw_flash_burst_counter_i225(hw,
831 ret_val = igc_write_erase_flash_command_i225(hw,
836 ret_val = igc_read_nvm_eerd(hw, current_offset, 1,
844 IGC_WRITE_REG(hw, IGC_I225_FLSWDATA,
849 ret_val = igc_poll_eerd_eewr_done(hw,
862 * @hw: pointer to the HW structure
865 igc_pool_flash_update_done_i225(struct igc_hw *hw)
873 reg = IGC_READ_REG(hw, IGC_EECD);
885 * @hw: pointer to the HW structure
892 igc_set_ltr_i225(struct igc_hw *hw, bool link)
902 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
907 if ((hw->phy.media_type == igc_media_type_copper) &&
908 !(hw->dev_spec._i225.eee_disable) &&
911 ltrc = IGC_READ_REG(hw, IGC_LTRC) | IGC_LTRC_EEEMS_EN;
912 IGC_WRITE_REG(hw, IGC_LTRC, ltrc);
916 tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) &
920 tw_system = (IGC_READ_REG(hw, IGC_EEE_SU) &
928 size = IGC_READ_REG(hw, IGC_RXPBS) & IGC_RXPBS_SIZE_I225_MASK;
931 if (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) {
932 size -= (IGC_READ_REG(hw, IGC_DMACR) &
941 size -= hw->dev_spec._i225.mtu;
966 ltrv = IGC_READ_REG(hw, IGC_LTRMINV);
970 IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv);
973 ltrv = IGC_READ_REG(hw, IGC_LTRMAXV);
977 IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv);
985 * @hw: pointer to the HW structure
992 igc_check_for_link_i225(struct igc_hw *hw)
994 struct igc_mac_info *mac = &hw->mac;
1014 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
1025 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
1037 igc_check_downshift_generic(hw);
1049 mac->ops.config_collision_dist(hw);
1056 ret_val = igc_config_fc_after_link_up_generic(hw);
1063 ret_val = igc_set_ltr_i225(hw, link);
1069 * @hw: pointer to the HW structure
1074 igc_init_function_pointers_i225(struct igc_hw *hw)
1076 igc_init_mac_ops_generic(hw);
1077 igc_init_phy_ops_generic(hw);
1078 igc_init_nvm_ops_generic(hw);
1079 hw->mac.ops.init_params = igc_init_mac_params_i225;
1080 hw->nvm.ops.init_params = igc_init_nvm_params_i225;
1081 hw->phy.ops.init_params = igc_init_phy_params_i225;
1084 /* igc_init_hw_i225 - Init hw for I225
1085 * @hw: pointer to the HW structure
1087 * Called to initialize hw for i225 hw family.
1090 igc_init_hw_i225(struct igc_hw *hw)
1096 ret_val = igc_init_hw_base(hw);
1102 * @hw: pointer to the HW structure
1111 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
1118 if (hw->mac.type != igc_i225 ||
1119 hw->phy.media_type != igc_media_type_copper)
1121 ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG);
1122 eeer = IGC_READ_REG(hw, IGC_EEER);
1125 if (!(hw->dev_spec._i225.eee_disable)) {
1126 uint32_t eee_su = IGC_READ_REG(hw, IGC_EEE_SU);
1155 IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg);
1156 IGC_WRITE_REG(hw, IGC_EEER, eeer);
1157 IGC_READ_REG(hw, IGC_IPCNFG);
1158 IGC_READ_REG(hw, IGC_EEER);