Lines Matching defs:sc
167 struct rge_softc *sc = (struct rge_softc *)self;
185 PCI_MAPREG_MEM_TYPE_64BIT, 0, &sc->rge_btag, &sc->rge_bhandle,
186 NULL, &sc->rge_bsize, 0)) {
188 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->rge_btag,
189 &sc->rge_bhandle, NULL, &sc->rge_bsize, 0)) {
191 0, &sc->rge_btag, &sc->rge_bhandle, NULL,
192 &sc->rge_bsize, 0)) {
204 q->q_sc = sc;
207 sc->sc_queues = q;
208 sc->sc_nqueues = 1;
215 sc->rge_flags |= RGE_FLAG_MSI;
221 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, rge_intr,
222 sc, sc->sc_dev.dv_xname);
223 if (sc->sc_ih == NULL) {
232 sc->sc_dmat = pa->pa_dmat;
233 sc->sc_pc = pa->pa_pc;
234 sc->sc_tag = pa->pa_tag;
237 hwrev = RGE_READ_4(sc, RGE_TXCFG) & RGE_TXCFG_HWREV;
240 sc->rge_type = MAC_CFG3;
243 sc->rge_type = MAC_CFG5;
246 sc->rge_type = MAC_CFG2_8126;
253 rge_config_imtype(sc, RGE_IMTYPE_SIM);
269 rge_chipinit(sc);
271 rge_get_macaddr(sc, eaddr);
274 memcpy(sc->sc_arpcom.ac_enaddr, eaddr, ETHER_ADDR_LEN);
276 if (rge_allocmem(sc))
279 ifp = &sc->sc_arpcom.ac_if;
280 ifp->if_softc = sc;
281 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
302 timeout_set(&sc->sc_timeout, rge_tick, sc);
303 task_set(&sc->sc_task, rge_txstart, sc);
306 ifmedia_init(&sc->sc_media, IFM_IMASK, rge_ifmedia_upd,
308 rge_add_media_types(sc);
309 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
310 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
311 sc->sc_media.ifm_media = sc->sc_media.ifm_cur->ifm_media;
317 rge_kstat_attach(sc);
325 struct rge_softc *sc = (struct rge_softc *)self;
331 rge_wol_power(sc);
341 struct rge_softc *sc = arg;
342 struct rge_queues *q = sc->sc_queues;
343 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
351 RGE_WRITE_4(sc, RGE_IMR, 0);
353 if (!(sc->rge_flags & RGE_FLAG_MSI)) {
354 if ((RGE_READ_4(sc, RGE_ISR) & sc->rge_intrs) == 0)
358 status = RGE_READ_4(sc, RGE_ISR);
360 RGE_WRITE_4(sc, RGE_ISR, status);
366 if (status & sc->rge_intrs) {
378 if (sc->rge_timerintr) {
384 rge_setup_intr(sc, RGE_IMTYPE_NONE);
394 RGE_WRITE_4(sc, RGE_TIMERCNT, 1);
401 rge_setup_intr(sc, RGE_IMTYPE_SIM);
404 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs);
410 rge_tx_list_sync(struct rge_softc *sc, struct rge_queues *q,
413 bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map,
421 struct rge_softc *sc = q->q_sc;
434 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m, BUS_DMA_NOWAIT);
440 bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m,
455 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize,
514 rge_tx_list_sync(sc, q, idx, txmap->dm_nsegs,
517 rge_tx_list_sync(sc, q, idx, RGE_TX_LIST_CNT - idx,
519 rge_tx_list_sync(sc, q, 0, cur + 1,
525 rge_tx_list_sync(sc, q, idx, 1, BUS_DMASYNC_POSTWRITE);
527 rge_tx_list_sync(sc, q, idx, 1, BUS_DMASYNC_PREWRITE);
535 struct rge_softc *sc = ifp->if_softc;
560 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
564 NULL, MCLBYTES, &sc->sc_queues->q_rx.rge_rx_ring);
567 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data);
572 rge_iff(sc);
584 struct rge_softc *sc = ifp->if_softc;
585 struct rge_queues *q = sc->sc_queues;
635 ifq_serialize(ifq, &sc->sc_task);
641 struct rge_softc *sc = ifp->if_softc;
643 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
652 struct rge_softc *sc = ifp->if_softc;
653 struct rge_queues *q = sc->sc_queues;
660 rge_set_macaddr(sc, sc->sc_arpcom.ac_enaddr);
666 rge_chipinit(sc);
668 if (rge_phy_config(sc))
671 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
673 RGE_CLRBIT_1(sc, 0xf1, 0x80);
674 rge_disable_aspm_clkreq(sc);
675 RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER,
679 RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO,
681 RGE_WRITE_4(sc, RGE_RXDESC_ADDR_HI,
683 RGE_WRITE_4(sc, RGE_TXDESC_ADDR_LO,
685 RGE_WRITE_4(sc, RGE_TXDESC_ADDR_HI,
689 if (sc->rge_type == MAC_CFG3)
691 else if (sc->rge_type == MAC_CFG5)
695 RGE_WRITE_4(sc, RGE_RXCFG, rxconf);
696 RGE_WRITE_4(sc, RGE_TXCFG, RGE_TXCFG_CONFIG);
698 val = rge_read_csi(sc, 0x70c) & ~0xff000000;
699 rge_write_csi(sc, 0x70c, val | 0x27000000);
701 if (sc->rge_type == MAC_CFG2_8126) {
703 val = rge_read_csi(sc, 0x890) & ~0x00000001;
704 rge_write_csi(sc, 0x890, val);
706 RGE_WRITE_2(sc, 0x0382, 0x221b);
708 RGE_WRITE_1(sc, RGE_RSS_CTRL, 0);
710 val = RGE_READ_2(sc, RGE_RXQUEUE_CTRL) & ~0x001c;
711 RGE_WRITE_2(sc, RGE_RXQUEUE_CTRL, val | (fls(sc->sc_nqueues) - 1) << 2);
713 RGE_CLRBIT_1(sc, RGE_CFG1, RGE_CFG1_SPEED_DOWN);
715 rge_write_mac_ocp(sc, 0xc140, 0xffff);
716 rge_write_mac_ocp(sc, 0xc142, 0xffff);
718 RGE_MAC_SETBIT(sc, 0xeb58, 0x0001);
720 if (sc->rge_type == MAC_CFG2_8126)
721 RGE_CLRBIT_1(sc, 0xd8, 0x02);
723 val = rge_read_mac_ocp(sc, 0xe614) & ~0x0700;
724 if (sc->rge_type == MAC_CFG3)
725 rge_write_mac_ocp(sc, 0xe614, val | 0x0300);
726 else if (sc->rge_type == MAC_CFG5)
727 rge_write_mac_ocp(sc, 0xe614, val | 0x0200);
729 rge_write_mac_ocp(sc, 0xe614, val | 0x0400);
731 val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0c00;
732 rge_write_mac_ocp(sc, 0xe63e, val |
733 ((fls(sc->sc_nqueues) - 1) & 0x03) << 10);
735 RGE_MAC_CLRBIT(sc, 0xe63e, 0x0030);
736 if (sc->rge_type != MAC_CFG5)
737 RGE_MAC_SETBIT(sc, 0xe63e, 0x0020);
739 RGE_MAC_CLRBIT(sc, 0xc0b4, 0x0001);
740 RGE_MAC_SETBIT(sc, 0xc0b4, 0x0001);
742 RGE_MAC_SETBIT(sc, 0xc0b4, 0x000c);
744 val = rge_read_mac_ocp(sc, 0xeb6a) & ~0x00ff;
745 rge_write_mac_ocp(sc, 0xeb6a, val | 0x0033);
747 val = rge_read_mac_ocp(sc, 0xeb50) & ~0x03e0;
748 rge_write_mac_ocp(sc, 0xeb50, val | 0x0040);
750 RGE_MAC_CLRBIT(sc, 0xe056, 0x00f0);
752 RGE_WRITE_1(sc, RGE_TDFNR, 0x10);
754 RGE_MAC_CLRBIT(sc, 0xe040, 0x1000);
756 val = rge_read_mac_ocp(sc, 0xea1c) & ~0x0003;
757 rge_write_mac_ocp(sc, 0xea1c, val | 0x0001);
759 rge_write_mac_ocp(sc, 0xe0c0, 0x4000);
761 RGE_MAC_SETBIT(sc, 0xe052, 0x0060);
762 RGE_MAC_CLRBIT(sc, 0xe052, 0x0088);
764 val = rge_read_mac_ocp(sc, 0xd430) & ~0x0fff;
765 rge_write_mac_ocp(sc, 0xd430, val | 0x045f);
767 RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_PFM_EN | RGE_DLLPR_TX_10M_PS_EN);
769 if (sc->rge_type == MAC_CFG3)
770 RGE_SETBIT_1(sc, RGE_MCUCMD, 0x01);
773 RGE_MAC_CLRBIT(sc, 0xe080, 0x0002);
775 if (sc->rge_type == MAC_CFG2_8126)
776 RGE_MAC_CLRBIT(sc, 0xea1c, 0x0304);
778 RGE_MAC_CLRBIT(sc, 0xea1c, 0x0004);
780 RGE_MAC_SETBIT(sc, 0xeb54, 0x0001);
782 RGE_MAC_CLRBIT(sc, 0xeb54, 0x0001);
784 RGE_CLRBIT_2(sc, 0x1880, 0x0030);
787 if (sc->rge_type != MAC_CFG3)
788 RGE_CLRBIT_1(sc, RGE_INT_CFG0, RGE_INT_CFG0_EN);
791 RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
792 RGE_WRITE_4(sc, RGE_TIMERINT1, 0);
793 RGE_WRITE_4(sc, RGE_TIMERINT2, 0);
794 RGE_WRITE_4(sc, RGE_TIMERINT3, 0);
796 num_miti = (sc->rge_type == MAC_CFG3) ? 64 : 32;
799 RGE_WRITE_4(sc, RGE_INTMITI(i), 0);
801 if (sc->rge_type == MAC_CFG5) {
802 RGE_CLRBIT_1(sc, RGE_INT_CFG0,
805 RGE_WRITE_2(sc, RGE_INT_CFG1, 0);
808 RGE_MAC_SETBIT(sc, 0xc0ac, 0x1f80);
810 rge_write_mac_ocp(sc, 0xe098, 0xc302);
812 RGE_MAC_CLRBIT(sc, 0xe032, 0x0003);
813 val = rge_read_csi(sc, 0x98) & ~0x0000ff00;
814 rge_write_csi(sc, 0x98, val);
816 val = rge_read_mac_ocp(sc, 0xe092) & ~0x00ff;
817 rge_write_mac_ocp(sc, 0xe092, val);
820 RGE_SETBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP);
822 RGE_SETBIT_2(sc, RGE_CPLUSCMD, RGE_CPLUSCMD_RXCSUM);
825 RGE_WRITE_2(sc, RGE_RXMAXSIZE, RGE_JUMBO_FRAMELEN);
828 RGE_CLRBIT_1(sc, RGE_PPSW, 0x08);
832 rge_iff(sc);
834 rge_disable_aspm_clkreq(sc);
836 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
842 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_TXENB | RGE_CMD_RXENB);
845 rge_setup_intr(sc, RGE_IMTYPE_SIM);
850 timeout_add_sec(&sc->sc_timeout, 1);
859 struct rge_softc *sc = ifp->if_softc;
860 struct rge_queues *q = sc->sc_queues;
863 timeout_del(&sc->sc_timeout);
867 sc->rge_timerintr = 0;
869 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV |
873 rge_hw_reset(sc);
875 RGE_MAC_CLRBIT(sc, 0xc0ac, 0x1f80);
877 intr_barrier(sc->sc_ih);
890 bus_dmamap_unload(sc->sc_dmat,
900 bus_dmamap_unload(sc->sc_dmat,
914 struct rge_softc *sc = ifp->if_softc;
915 struct ifmedia *ifm = &sc->sc_media;
922 RGE_PHY_CLRBIT(sc, 0xa428, 0x0200);
923 RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001);
924 if (sc->rge_type == MAC_CFG2_8126)
925 RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0002);
927 val = rge_read_phy_ocp(sc, 0xa5d4);
929 if (sc->rge_type == MAC_CFG2_8126)
937 val |= (sc->rge_type != MAC_CFG2_8126) ?
952 gig = rge_read_phy(sc, 0, MII_100T2CR) &
960 gig = rge_read_phy(sc, 0, MII_100T2CR) &
967 printf("%s: unsupported media type\n", sc->sc_dev.dv_xname);
971 rge_write_phy(sc, 0, MII_ANAR, anar | ANAR_PAUSE_ASYM | ANAR_FC);
972 rge_write_phy(sc, 0, MII_100T2CR, gig);
973 rge_write_phy_ocp(sc, 0xa5d4, val);
974 rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
986 struct rge_softc *sc = ifp->if_softc;
992 if (rge_get_link_status(sc)) {
995 status = RGE_READ_2(sc, RGE_PHYSTAT);
1019 rge_allocmem(struct rge_softc *sc)
1021 struct rge_queues *q = sc->sc_queues;
1025 error = bus_dmamap_create(sc->sc_dmat, RGE_TX_LIST_SZ, 1,
1029 printf("%s: can't create TX list map\n", sc->sc_dev.dv_xname);
1032 error = bus_dmamem_alloc(sc->sc_dmat, RGE_TX_LIST_SZ, RGE_ALIGN, 0,
1036 printf("%s: can't alloc TX list\n", sc->sc_dev.dv_xname);
1041 error = bus_dmamem_map(sc->sc_dmat, &q->q_tx.rge_tx_listseg,
1045 printf("%s: can't map TX dma buffers\n", sc->sc_dev.dv_xname);
1046 bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg,
1050 error = bus_dmamap_load(sc->sc_dmat, q->q_tx.rge_tx_list_map,
1053 printf("%s: can't load TX dma map\n", sc->sc_dev.dv_xname);
1054 bus_dmamap_destroy(sc->sc_dmat, q->q_tx.rge_tx_list_map);
1055 bus_dmamem_unmap(sc->sc_dmat,
1057 bus_dmamem_free(sc->sc_dmat, &q->q_tx.rge_tx_listseg,
1064 error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN,
1070 sc->sc_dev.dv_xname);
1076 error = bus_dmamap_create(sc->sc_dmat, RGE_RX_LIST_SZ, 1,
1080 printf("%s: can't create RX list map\n", sc->sc_dev.dv_xname);
1083 error = bus_dmamem_alloc(sc->sc_dmat, RGE_RX_LIST_SZ, RGE_ALIGN, 0,
1087 printf("%s: can't alloc RX list\n", sc->sc_dev.dv_xname);
1092 error = bus_dmamem_map(sc->sc_dmat, &q->q_rx.rge_rx_listseg,
1096 printf("%s: can't map RX dma buffers\n", sc->sc_dev.dv_xname);
1097 bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg,
1101 error = bus_dmamap_load(sc->sc_dmat, q->q_rx.rge_rx_list_map,
1104 printf("%s: can't load RX dma map\n", sc->sc_dev.dv_xname);
1105 bus_dmamap_destroy(sc->sc_dmat, q->q_rx.rge_rx_list_map);
1106 bus_dmamem_unmap(sc->sc_dmat,
1108 bus_dmamem_free(sc->sc_dmat, &q->q_rx.rge_rx_listseg,
1115 error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, 1,
1120 sc->sc_dev.dv_xname);
1134 struct rge_softc *sc = q->q_sc;
1153 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)) {
1158 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize,
1174 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,
1178 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,
1183 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,
1221 struct rge_softc *sc = q->q_sc;
1233 bus_dmamap_sync(sc->sc_dmat, q->q_tx.rge_tx_list_map, 0,
1243 struct rge_softc *sc = q->q_sc;
1246 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1259 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,
1264 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,
1271 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_dmamap, 0,
1273 bus_dmamap_unload(sc->sc_dmat, rxq->rxq_dmamap);
1351 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,
1355 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,
1360 bus_dmamap_sync(sc->sc_dmat, q->q_rx.rge_rx_list_map,
1378 struct rge_softc *sc = q->q_sc;
1379 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1393 rge_tx_list_sync(sc, q, cur, 1, BUS_DMASYNC_POSTREAD);
1395 rge_tx_list_sync(sc, q, cur, 1, BUS_DMASYNC_PREREAD);
1401 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 0,
1403 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap);
1421 rge_tx_list_sync(sc, q, cons, idx - cons,
1424 rge_tx_list_sync(sc, q, cons, RGE_TX_LIST_CNT - cons,
1426 rge_tx_list_sync(sc, q, 0, idx,
1435 ifq_serialize(&ifp->if_snd, &sc->sc_task);
1443 rge_reset(struct rge_softc *sc)
1447 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV |
1452 RGE_SETBIT_1(sc, RGE_PPSW, 0x08);
1455 RGE_SETBIT_1(sc, RGE_CMD, RGE_CMD_STOPREQ);
1456 if (sc->rge_type != MAC_CFG2_8126) {
1459 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_STOPREQ))
1466 if ((RGE_READ_1(sc, RGE_MCUCMD) & (RGE_MCUCMD_RXFIFO_EMPTY |
1471 if (sc->rge_type != MAC_CFG3) {
1474 if ((RGE_READ_2(sc, RGE_IM) & 0x0103) == 0x0103)
1482 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET);
1486 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_RESET))
1490 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);
1494 rge_iff(struct rge_softc *sc)
1496 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1497 struct arpcom *ac = &sc->sc_arpcom;
1504 rxfilt = RGE_READ_4(sc, RGE_RXCFG);
1539 RGE_WRITE_4(sc, RGE_RXCFG, rxfilt);
1540 RGE_WRITE_4(sc, RGE_MAR0, swap32(hashes[1]));
1541 RGE_WRITE_4(sc, RGE_MAR4, swap32(hashes[0]));
1545 rge_chipinit(struct rge_softc *sc)
1547 rge_exit_oob(sc);
1548 rge_set_phy_power(sc, 1);
1549 rge_hw_init(sc);
1550 rge_hw_reset(sc);
1554 rge_set_phy_power(struct rge_softc *sc, int on)
1559 RGE_SETBIT_1(sc, RGE_PMCH, 0xc0);
1561 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN);
1564 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 3)
1569 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN);
1570 RGE_CLRBIT_1(sc, RGE_PMCH, 0x80);
1571 RGE_CLRBIT_1(sc, RGE_PPSW, 0x40);
1576 rge_ephy_config(struct rge_softc *sc)
1578 switch (sc->rge_type) {
1580 rge_ephy_config_mac_cfg3(sc);
1583 rge_ephy_config_mac_cfg5(sc);
1591 rge_ephy_config_mac_cfg3(struct rge_softc *sc)
1597 rge_write_ephy(sc, rtl8125_mac_cfg3_ephy[i].reg,
1600 val = rge_read_ephy(sc, 0x002a) & ~0x7000;
1601 rge_write_ephy(sc, 0x002a, val | 0x3000);
1602 RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040);
1603 RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00);
1604 RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000);
1605 rge_write_ephy(sc, 0x0002, 0x6042);
1606 rge_write_ephy(sc, 0x0006, 0x0014);
1607 val = rge_read_ephy(sc, 0x006a) & ~0x7000;
1608 rge_write_ephy(sc, 0x006a, val | 0x3000);
1609 RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040);
1610 RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00);
1611 RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000);
1612 rge_write_ephy(sc, 0x0042, 0x6042);
1613 rge_write_ephy(sc, 0x0046, 0x0014);
1617 rge_ephy_config_mac_cfg5(struct rge_softc *sc)
1622 rge_write_ephy(sc, rtl8125_mac_cfg5_ephy[i].reg,
1627 rge_phy_config(struct rge_softc *sc)
1631 rge_ephy_config(sc);
1634 rge_write_phy(sc, 0, MII_ANAR,
1635 rge_read_phy(sc, 0, MII_ANAR) &
1637 rge_write_phy(sc, 0, MII_100T2CR,
1638 rge_read_phy(sc, 0, MII_100T2CR) &
1640 if (sc->rge_type == MAC_CFG2_8126)
1641 RGE_PHY_CLRBIT(sc, 0xa5d4, RGE_ADV_2500TFDX | RGE_ADV_5000TFDX);
1643 RGE_PHY_CLRBIT(sc, 0xa5d4, RGE_ADV_2500TFDX);
1644 rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
1647 if (!(rge_read_phy(sc, 0, MII_BMCR) & BMCR_RESET))
1652 printf("%s: PHY reset failed\n", sc->sc_dev.dv_xname);
1657 rge_write_phy_ocp(sc, 0xa436, 0x801e);
1658 sc->rge_mcodever = rge_read_phy_ocp(sc, 0xa438);
1660 switch (sc->rge_type) {
1662 rge_phy_config_mac_cfg2_8126(sc);
1665 rge_phy_config_mac_cfg3(sc);
1668 rge_phy_config_mac_cfg5(sc);
1674 RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000);
1677 RGE_MAC_CLRBIT(sc, 0xe040, 0x0003);
1678 if (sc->rge_type == MAC_CFG3) {
1679 RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006);
1680 RGE_PHY_CLRBIT(sc, 0xa432, 0x0010);
1681 } else if (sc->rge_type == MAC_CFG5)
1682 RGE_PHY_SETBIT(sc, 0xa432, 0x0010);
1684 RGE_PHY_CLRBIT(sc, 0xa5d0, 0x0006);
1685 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001);
1686 if (sc->rge_type == MAC_CFG2_8126)
1687 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002);
1688 RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010);
1689 RGE_PHY_CLRBIT(sc, 0xa428, 0x0080);
1690 RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200);
1693 RGE_MAC_CLRBIT(sc, 0xe052, 0x0001);
1694 RGE_PHY_CLRBIT(sc, 0xa442, 0x3000);
1695 RGE_PHY_CLRBIT(sc, 0xa430, 0x8000);
1701 rge_phy_config_mac_cfg2_8126(struct rge_softc *sc)
1718 rge_phy_config_mcu(sc, RGE_MAC_CFG2_8126_MCODE_VER);
1720 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1721 rge_write_phy_ocp(sc, 0xa436, 0x80bf);
1722 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1723 rge_write_phy_ocp(sc, 0xa438, val | 0xed00);
1724 rge_write_phy_ocp(sc, 0xa436, 0x80cd);
1725 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1726 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
1727 rge_write_phy_ocp(sc, 0xa436, 0x80d1);
1728 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1729 rge_write_phy_ocp(sc, 0xa438, val | 0xc800);
1730 rge_write_phy_ocp(sc, 0xa436, 0x80d4);
1731 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1732 rge_write_phy_ocp(sc, 0xa438, val | 0xc800);
1733 rge_write_phy_ocp(sc, 0xa436, 0x80e1);
1734 rge_write_phy_ocp(sc, 0xa438, 0x10cc);
1735 rge_write_phy_ocp(sc, 0xa436, 0x80e5);
1736 rge_write_phy_ocp(sc, 0xa438, 0x4f0c);
1737 rge_write_phy_ocp(sc, 0xa436, 0x8387);
1738 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1739 rge_write_phy_ocp(sc, 0xa438, val | 0x4700);
1740 val = rge_read_phy_ocp(sc, 0xa80c) & ~0x00c0;
1741 rge_write_phy_ocp(sc, 0xa80c, val | 0x0080);
1742 RGE_PHY_CLRBIT(sc, 0xac90, 0x0010);
1743 RGE_PHY_CLRBIT(sc, 0xad2c, 0x8000);
1744 rge_write_phy_ocp(sc, 0xb87c, 0x8321);
1745 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1746 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
1747 RGE_PHY_SETBIT(sc, 0xacf8, 0x000c);
1748 rge_write_phy_ocp(sc, 0xa436, 0x8183);
1749 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1750 rge_write_phy_ocp(sc, 0xa438, val | 0x5900);
1751 RGE_PHY_SETBIT(sc, 0xad94, 0x0020);
1752 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800);
1753 RGE_PHY_SETBIT(sc, 0xb648, 0x4000);
1754 rge_write_phy_ocp(sc, 0xb87c, 0x839e);
1755 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1756 rge_write_phy_ocp(sc, 0xb87e, val | 0x2f00);
1757 rge_write_phy_ocp(sc, 0xb87c, 0x83f2);
1758 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1759 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
1760 RGE_PHY_SETBIT(sc, 0xada0, 0x0002);
1761 rge_write_phy_ocp(sc, 0xb87c, 0x80f3);
1762 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1763 rge_write_phy_ocp(sc, 0xb87e, val | 0x9900);
1764 rge_write_phy_ocp(sc, 0xb87c, 0x8126);
1765 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1766 rge_write_phy_ocp(sc, 0xb87e, val | 0xc100);
1767 rge_write_phy_ocp(sc, 0xb87c, 0x893a);
1768 rge_write_phy_ocp(sc, 0xb87e, 0x8080);
1769 rge_write_phy_ocp(sc, 0xb87c, 0x8647);
1770 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1771 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
1772 rge_write_phy_ocp(sc, 0xb87c, 0x862c);
1773 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1774 rge_write_phy_ocp(sc, 0xb87e, val | 0x1200);
1775 rge_write_phy_ocp(sc, 0xb87c, 0x864a);
1776 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1777 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
1778 rge_write_phy_ocp(sc, 0xb87c, 0x80a0);
1779 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc);
1780 rge_write_phy_ocp(sc, 0xb87c, 0x805e);
1781 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc);
1782 rge_write_phy_ocp(sc, 0xb87c, 0x8056);
1783 rge_write_phy_ocp(sc, 0xb87e, 0x3077);
1784 rge_write_phy_ocp(sc, 0xb87c, 0x8058);
1785 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1786 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00);
1787 rge_write_phy_ocp(sc, 0xb87c, 0x8098);
1788 rge_write_phy_ocp(sc, 0xb87e, 0x3077);
1789 rge_write_phy_ocp(sc, 0xb87c, 0x809a);
1790 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1791 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00);
1792 rge_write_phy_ocp(sc, 0xb87c, 0x8052);
1793 rge_write_phy_ocp(sc, 0xb87e, 0x3733);
1794 rge_write_phy_ocp(sc, 0xb87c, 0x8094);
1795 rge_write_phy_ocp(sc, 0xb87e, 0x3733);
1796 rge_write_phy_ocp(sc, 0xb87c, 0x807f);
1797 rge_write_phy_ocp(sc, 0xb87e, 0x7c75);
1798 rge_write_phy_ocp(sc, 0xb87c, 0x803d);
1799 rge_write_phy_ocp(sc, 0xb87e, 0x7c75);
1800 rge_write_phy_ocp(sc, 0xb87c, 0x8036);
1801 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1802 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
1803 rge_write_phy_ocp(sc, 0xb87c, 0x8078);
1804 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1805 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
1806 rge_write_phy_ocp(sc, 0xb87c, 0x8031);
1807 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1808 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300);
1809 rge_write_phy_ocp(sc, 0xb87c, 0x8073);
1810 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1811 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300);
1812 val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00;
1813 rge_write_phy_ocp(sc, 0xae06, val | 0x7c00);
1814 rge_write_phy_ocp(sc, 0xb87c, 0x89D1);
1815 rge_write_phy_ocp(sc, 0xb87e, 0x0004);
1816 rge_write_phy_ocp(sc, 0xa436, 0x8fbd);
1817 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1818 rge_write_phy_ocp(sc, 0xa438, val | 0x0a00);
1819 rge_write_phy_ocp(sc, 0xa436, 0x8fbe);
1820 rge_write_phy_ocp(sc, 0xa438, 0x0d09);
1821 rge_write_phy_ocp(sc, 0xb87c, 0x89cd);
1822 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f);
1823 rge_write_phy_ocp(sc, 0xb87c, 0x89cf);
1824 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f);
1825 rge_write_phy_ocp(sc, 0xb87c, 0x83a4);
1826 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
1827 rge_write_phy_ocp(sc, 0xb87c, 0x83a6);
1828 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
1829 rge_write_phy_ocp(sc, 0xb87c, 0x83c0);
1830 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
1831 rge_write_phy_ocp(sc, 0xb87c, 0x83c2);
1832 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
1833 rge_write_phy_ocp(sc, 0xb87c, 0x8414);
1834 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
1835 rge_write_phy_ocp(sc, 0xb87c, 0x8416);
1836 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
1837 rge_write_phy_ocp(sc, 0xb87c, 0x83f8);
1838 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
1839 rge_write_phy_ocp(sc, 0xb87c, 0x83fa);
1840 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
1842 rge_patch_phy_mcu(sc, 1);
1843 val = rge_read_phy_ocp(sc, 0xbd96) & ~0x1f00;
1844 rge_write_phy_ocp(sc, 0xbd96, val | 0x1000);
1845 val = rge_read_phy_ocp(sc, 0xbf1c) & ~0x0007;
1846 rge_write_phy_ocp(sc, 0xbf1c, val | 0x0007);
1847 RGE_PHY_CLRBIT(sc, 0xbfbe, 0x8000);
1848 val = rge_read_phy_ocp(sc, 0xbf40) & ~0x0380;
1849 rge_write_phy_ocp(sc, 0xbf40, val | 0x0280);
1850 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0080;
1851 rge_write_phy_ocp(sc, 0xbf90, val | 0x0060);
1852 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0010;
1853 rge_write_phy_ocp(sc, 0xbf90, val | 0x000c);
1854 rge_patch_phy_mcu(sc, 0);
1856 rge_write_phy_ocp(sc, 0xa436, 0x843b);
1857 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1858 rge_write_phy_ocp(sc, 0xa438, val | 0x2000);
1859 rge_write_phy_ocp(sc, 0xa436, 0x843d);
1860 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1861 rge_write_phy_ocp(sc, 0xa438, val | 0x2000);
1862 RGE_PHY_CLRBIT(sc, 0xb516, 0x007f);
1863 RGE_PHY_CLRBIT(sc, 0xbf80, 0x0030);
1865 rge_write_phy_ocp(sc, 0xa436, 0x8188);
1867 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]);
1869 rge_write_phy_ocp(sc, 0xb87c, 0x8015);
1870 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1871 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
1872 rge_write_phy_ocp(sc, 0xb87c, 0x8ffd);
1873 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1874 rge_write_phy_ocp(sc, 0xb87e, val | 0);
1875 rge_write_phy_ocp(sc, 0xb87c, 0x8fff);
1876 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1877 rge_write_phy_ocp(sc, 0xb87e, val | 0x7f00);
1878 rge_write_phy_ocp(sc, 0xb87c, 0x8ffb);
1879 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1880 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1881 rge_write_phy_ocp(sc, 0xb87c, 0x8fe9);
1882 rge_write_phy_ocp(sc, 0xb87e, 0x0002);
1883 rge_write_phy_ocp(sc, 0xb87c, 0x8fef);
1884 rge_write_phy_ocp(sc, 0xb87e, 0x00a5);
1885 rge_write_phy_ocp(sc, 0xb87c, 0x8ff1);
1886 rge_write_phy_ocp(sc, 0xb87e, 0x0106);
1887 rge_write_phy_ocp(sc, 0xb87c, 0x8fe1);
1888 rge_write_phy_ocp(sc, 0xb87e, 0x0102);
1889 rge_write_phy_ocp(sc, 0xb87c, 0x8fe3);
1890 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1891 rge_write_phy_ocp(sc, 0xb87e, val | 0x0400);
1892 RGE_PHY_SETBIT(sc, 0xa654, 0x0800);
1893 RGE_PHY_CLRBIT(sc, 0xa654, 0x0003);
1894 rge_write_phy_ocp(sc, 0xac3a, 0x5851);
1895 val = rge_read_phy_ocp(sc, 0xac3c) & ~0xd000;
1896 rge_write_phy_ocp(sc, 0xac3c, val | 0x2000);
1897 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0200;
1898 rge_write_phy_ocp(sc, 0xac42, val | 0x01c0);
1899 RGE_PHY_CLRBIT(sc, 0xac3e, 0xe000);
1900 RGE_PHY_CLRBIT(sc, 0xac42, 0x0038);
1901 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0002;
1902 rge_write_phy_ocp(sc, 0xac42, val | 0x0005);
1903 rge_write_phy_ocp(sc, 0xac1a, 0x00db);
1904 rge_write_phy_ocp(sc, 0xade4, 0x01b5);
1905 RGE_PHY_CLRBIT(sc, 0xad9c, 0x0c00);
1906 rge_write_phy_ocp(sc, 0xb87c, 0x814b);
1907 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1908 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
1909 rge_write_phy_ocp(sc, 0xb87c, 0x814d);
1910 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1911 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
1912 rge_write_phy_ocp(sc, 0xb87c, 0x814f);
1913 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1914 rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00);
1915 rge_write_phy_ocp(sc, 0xb87c, 0x8142);
1916 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1917 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1918 rge_write_phy_ocp(sc, 0xb87c, 0x8144);
1919 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1920 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1921 rge_write_phy_ocp(sc, 0xb87c, 0x8150);
1922 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1923 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1924 rge_write_phy_ocp(sc, 0xb87c, 0x8118);
1925 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1926 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
1927 rge_write_phy_ocp(sc, 0xb87c, 0x811a);
1928 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1929 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
1930 rge_write_phy_ocp(sc, 0xb87c, 0x811c);
1931 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1932 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
1933 rge_write_phy_ocp(sc, 0xb87c, 0x810f);
1934 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1935 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1936 rge_write_phy_ocp(sc, 0xb87c, 0x8111);
1937 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1938 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1939 rge_write_phy_ocp(sc, 0xb87c, 0x811d);
1940 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1941 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1942 RGE_PHY_SETBIT(sc, 0xac36, 0x1000);
1943 RGE_PHY_CLRBIT(sc, 0xad1c, 0x0100);
1944 val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0;
1945 rge_write_phy_ocp(sc, 0xade8, val | 0x1400);
1946 rge_write_phy_ocp(sc, 0xb87c, 0x864b);
1947 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1948 rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00);
1950 rge_write_phy_ocp(sc, 0xa436, 0x8f97);
1952 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]);
1954 RGE_PHY_SETBIT(sc, 0xad9c, 0x0020);
1955 rge_write_phy_ocp(sc, 0xb87c, 0x8122);
1956 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1957 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
1959 rge_write_phy_ocp(sc, 0xb87c, 0x82c8);
1961 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]);
1963 rge_write_phy_ocp(sc, 0xb87c, 0x80ef);
1964 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1965 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
1967 rge_write_phy_ocp(sc, 0xb87c, 0x82a0);
1969 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]);
1971 rge_write_phy_ocp(sc, 0xa436, 0x8018);
1972 RGE_PHY_SETBIT(sc, 0xa438, 0x2000);
1973 rge_write_phy_ocp(sc, 0xb87c, 0x8fe4);
1974 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1975 rge_write_phy_ocp(sc, 0xb87e, val | 0);
1976 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0;
1977 rge_write_phy_ocp(sc, 0xb54c, val | 0x3700);
1981 rge_phy_config_mac_cfg3(struct rge_softc *sc)
1997 rge_phy_config_mcu(sc, RGE_MAC_CFG3_MCODE_VER);
1999 RGE_PHY_SETBIT(sc, 0xad4e, 0x0010);
2000 val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff;
2001 rge_write_phy_ocp(sc, 0xad16, val | 0x03ff);
2002 val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f;
2003 rge_write_phy_ocp(sc, 0xad32, val | 0x0006);
2004 RGE_PHY_CLRBIT(sc, 0xac08, 0x1000);
2005 RGE_PHY_CLRBIT(sc, 0xac08, 0x0100);
2006 val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003;
2007 rge_write_phy_ocp(sc, 0xacc0, val | 0x0002);
2008 val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0;
2009 rge_write_phy_ocp(sc, 0xad40, val | 0x0040);
2010 val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007;
2011 rge_write_phy_ocp(sc, 0xad40, val | 0x0004);
2012 RGE_PHY_CLRBIT(sc, 0xac14, 0x0080);
2013 RGE_PHY_CLRBIT(sc, 0xac80, 0x0300);
2014 val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007;
2015 rge_write_phy_ocp(sc, 0xac5e, val | 0x0002);
2016 rge_write_phy_ocp(sc, 0xad4c, 0x00a8);
2017 rge_write_phy_ocp(sc, 0xac5c, 0x01ff);
2018 val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0;
2019 rge_write_phy_ocp(sc, 0xac8a, val | 0x0030);
2020 rge_write_phy_ocp(sc, 0xb87c, 0x8157);
2021 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
2022 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
2023 rge_write_phy_ocp(sc, 0xb87c, 0x8159);
2024 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
2025 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
2026 rge_write_phy_ocp(sc, 0xb87c, 0x80a2);
2027 rge_write_phy_ocp(sc, 0xb87e, 0x0153);
2028 rge_write_phy_ocp(sc, 0xb87c, 0x809c);
2029 rge_write_phy_ocp(sc, 0xb87e, 0x0153);
2031 rge_write_phy_ocp(sc, 0xa436, 0x81b3);
2033 rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]);
2035 rge_write_phy_ocp(sc, 0xa438, 0);
2036 rge_write_phy_ocp(sc, 0xa436, 0x8257);
2037 rge_write_phy_ocp(sc, 0xa438, 0x020f);
2038 rge_write_phy_ocp(sc, 0xa436, 0x80ea);
2039 rge_write_phy_ocp(sc, 0xa438, 0x7843);
2041 rge_patch_phy_mcu(sc, 1);
2042 RGE_PHY_CLRBIT(sc, 0xb896, 0x0001);
2043 RGE_PHY_CLRBIT(sc, 0xb892, 0xff00);
2045 rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]);
2046 rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]);
2048 RGE_PHY_SETBIT(sc, 0xb896, 0x0001);
2049 rge_patch_phy_mcu(sc, 0);
2051 RGE_PHY_SETBIT(sc, 0xd068, 0x2000);
2052 rge_write_phy_ocp(sc, 0xa436, 0x81a2);
2053 RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
2054 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00;
2055 rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00);
2056 RGE_PHY_CLRBIT(sc, 0xa454, 0x0001);
2057 RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020);
2058 RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010);
2059 RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001);
2060 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
2061 RGE_PHY_SETBIT(sc, 0xa424, 0x0008);
2065 rge_phy_config_mac_cfg5(struct rge_softc *sc)
2070 rge_phy_config_mcu(sc, RGE_MAC_CFG5_MCODE_VER);
2072 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
2073 val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0;
2074 rge_write_phy_ocp(sc, 0xac46, val | 0x0090);
2075 val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003;
2076 rge_write_phy_ocp(sc, 0xad30, val | 0x0001);
2077 rge_write_phy_ocp(sc, 0xb87c, 0x80f5);
2078 rge_write_phy_ocp(sc, 0xb87e, 0x760e);
2079 rge_write_phy_ocp(sc, 0xb87c, 0x8107);
2080 rge_write_phy_ocp(sc, 0xb87e, 0x360e);
2081 rge_write_phy_ocp(sc, 0xb87c, 0x8551);
2082 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
2083 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
2084 val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000;
2085 rge_write_phy_ocp(sc, 0xbf00, val | 0xa000);
2086 val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00;
2087 rge_write_phy_ocp(sc, 0xbf46, val | 0x0300);
2089 rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6);
2090 rge_write_phy_ocp(sc, 0xa438, 0x2417);
2092 RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040);
2093 val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000;
2094 rge_write_phy_ocp(sc, 0xbf84, val | 0xa000);
2095 rge_write_phy_ocp(sc, 0xa436, 0x8170);
2096 val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700;
2097 rge_write_phy_ocp(sc, 0xa438, val | 0xd800);
2098 RGE_PHY_SETBIT(sc, 0xa424, 0x0008);
2102 rge_phy_config_mcu(struct rge_softc *sc, uint16_t mcode_version)
2104 if (sc->rge_mcodever != mcode_version) {
2107 rge_patch_phy_mcu(sc, 1);
2109 if (sc->rge_type == MAC_CFG3) {
2110 rge_write_phy_ocp(sc, 0xa436, 0x8024);
2111 rge_write_phy_ocp(sc, 0xa438, 0x8601);
2112 rge_write_phy_ocp(sc, 0xa436, 0xb82e);
2113 rge_write_phy_ocp(sc, 0xa438, 0x0001);
2115 RGE_PHY_SETBIT(sc, 0xb820, 0x0080);
2118 rge_write_phy_ocp(sc,
2123 RGE_PHY_CLRBIT(sc, 0xb820, 0x0080);
2125 rge_write_phy_ocp(sc, 0xa436, 0);
2126 rge_write_phy_ocp(sc, 0xa438, 0);
2127 RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001);
2128 rge_write_phy_ocp(sc, 0xa436, 0x8024);
2129 rge_write_phy_ocp(sc, 0xa438, 0);
2130 } else if (sc->rge_type == MAC_CFG5) {
2132 rge_write_phy_ocp(sc,
2136 } else if (sc->rge_type == MAC_CFG2_8126) {
2138 rge_write_phy_ocp(sc,
2144 rge_patch_phy_mcu(sc, 0);
2147 rge_write_phy_ocp(sc, 0xa436, 0x801e);
2148 rge_write_phy_ocp(sc, 0xa438, mcode_version);
2153 rge_set_macaddr(struct rge_softc *sc, const uint8_t *addr)
2155 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2156 RGE_WRITE_4(sc, RGE_MAC0,
2158 RGE_WRITE_4(sc, RGE_MAC4,
2160 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2164 rge_get_macaddr(struct rge_softc *sc, uint8_t *addr)
2169 addr[i] = RGE_READ_1(sc, RGE_MAC0 + i);
2171 *(uint32_t *)&addr[0] = RGE_READ_4(sc, RGE_ADDR0);
2172 *(uint16_t *)&addr[4] = RGE_READ_2(sc, RGE_ADDR1);
2174 rge_set_macaddr(sc, addr);
2178 rge_hw_init(struct rge_softc *sc)
2183 rge_disable_aspm_clkreq(sc);
2184 RGE_CLRBIT_1(sc, 0xf1, 0x80);
2187 RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010);
2190 rge_disable_aspm_clkreq(sc);
2191 rge_write_mac_ocp(sc, 0xfc48, 0);
2193 rge_write_mac_ocp(sc, reg, 0);
2195 rge_write_mac_ocp(sc, 0xfc26, 0);
2197 if (sc->rge_type == MAC_CFG3) {
2199 rge_switch_mcu_ram_page(sc, npages);
2202 rge_write_mac_ocp(sc,
2206 rge_write_mac_ocp(sc,
2210 rge_write_mac_ocp(sc,
2215 rge_write_mac_ocp(sc, 0xf9f8, 0x6486);
2216 rge_write_mac_ocp(sc, 0xf9fa, 0x0b15);
2217 rge_write_mac_ocp(sc, 0xf9fc, 0x090e);
2218 rge_write_mac_ocp(sc, 0xf9fe, 0x1139);
2221 rge_write_mac_ocp(sc, 0xfc26, 0x8000);
2222 rge_write_mac_ocp(sc, 0xfc2a, 0x0540);
2223 rge_write_mac_ocp(sc, 0xfc2e, 0x0a06);
2224 rge_write_mac_ocp(sc, 0xfc30, 0x0eb8);
2225 rge_write_mac_ocp(sc, 0xfc32, 0x3a5c);
2226 rge_write_mac_ocp(sc, 0xfc34, 0x10a8);
2227 rge_write_mac_ocp(sc, 0xfc40, 0x0d54);
2228 rge_write_mac_ocp(sc, 0xfc42, 0x0e24);
2229 rge_write_mac_ocp(sc, 0xfc48, 0x307a);
2230 } else if (sc->rge_type == MAC_CFG5) {
2231 rge_switch_mcu_ram_page(sc, 0);
2233 rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg,
2239 if (sc->rge_type == MAC_CFG3)
2240 rge_disable_phy_ocp_pwrsave(sc);
2243 rge_write_csi(sc, 0x108,
2244 rge_read_csi(sc, 0x108) | 0x00100000);
2248 rge_hw_reset(struct rge_softc *sc)
2251 RGE_WRITE_4(sc, RGE_IMR, 0);
2252 RGE_WRITE_4(sc, RGE_ISR, RGE_READ_4(sc, RGE_ISR));
2255 RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
2256 RGE_WRITE_4(sc, RGE_TIMERINT1, 0);
2257 RGE_WRITE_4(sc, RGE_TIMERINT2, 0);
2258 RGE_WRITE_4(sc, RGE_TIMERINT3, 0);
2260 rge_reset(sc);
2264 rge_disable_phy_ocp_pwrsave(struct rge_softc *sc)
2266 if (rge_read_phy_ocp(sc, 0xc416) != 0x0500) {
2267 rge_patch_phy_mcu(sc, 1);
2268 rge_write_phy_ocp(sc, 0xc416, 0);
2269 rge_write_phy_ocp(sc, 0xc416, 0x0500);
2270 rge_patch_phy_mcu(sc, 0);
2275 rge_patch_phy_mcu(struct rge_softc *sc, int set)
2280 RGE_PHY_SETBIT(sc, 0xb820, 0x0010);
2282 RGE_PHY_CLRBIT(sc, 0xb820, 0x0010);
2286 if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) != 0)
2289 if (!(rge_read_phy_ocp(sc, 0xb800) & 0x0040))
2296 sc->sc_dev.dv_xname);
2300 rge_add_media_types(struct rge_softc *sc)
2302 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL);
2303 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2304 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL);
2305 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2306 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T, 0, NULL);
2307 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2308 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T, 0, NULL);
2309 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);
2311 if (sc->rge_type == MAC_CFG2_8126) {
2312 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T, 0, NULL);
2313 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T | IFM_FDX,
2319 rge_config_imtype(struct rge_softc *sc, int imtype)
2323 sc->rge_intrs = RGE_INTRS;
2326 sc->rge_intrs = RGE_INTRS_TIMER;
2329 panic("%s: unknown imtype %d", sc->sc_dev.dv_xname, imtype);
2334 rge_disable_aspm_clkreq(struct rge_softc *sc)
2336 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2337 if (sc->rge_type == MAC_CFG2_8126)
2338 RGE_CLRBIT_1(sc, RGE_INT_CFG0, 0x08);
2340 RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN);
2341 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS);
2342 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2346 rge_disable_hw_im(struct rge_softc *sc)
2348 RGE_WRITE_2(sc, RGE_IM, 0);
2352 rge_disable_sim_im(struct rge_softc *sc)
2354 RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
2355 sc->rge_timerintr = 0;
2359 rge_setup_sim_im(struct rge_softc *sc)
2361 RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600);
2362 RGE_WRITE_4(sc, RGE_TIMERCNT, 1);
2363 sc->rge_timerintr = 1;
2367 rge_setup_intr(struct rge_softc *sc, int imtype)
2369 rge_config_imtype(sc, imtype);
2372 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs);
2376 rge_disable_sim_im(sc);
2377 rge_disable_hw_im(sc);
2380 rge_disable_hw_im(sc);
2381 rge_setup_sim_im(sc);
2384 panic("%s: unknown imtype %d", sc->sc_dev.dv_xname, imtype);
2389 rge_switch_mcu_ram_page(struct rge_softc *sc, int page)
2393 val = rge_read_mac_ocp(sc, 0xe446) & ~0x0003;
2395 rge_write_mac_ocp(sc, 0xe446, val);
2399 rge_exit_oob(struct rge_softc *sc)
2403 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV |
2408 rge_write_mac_ocp(sc, 0xc0bc, 0x00ff);
2410 rge_reset(sc);
2413 RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB);
2415 RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000);
2419 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200)
2423 rge_write_mac_ocp(sc, 0xc0aa, 0x07d0);
2424 rge_write_mac_ocp(sc, 0xc0a6, 0x01b5);
2425 rge_write_mac_ocp(sc, 0xc01e, 0x5555);
2429 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200)
2433 if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) {
2435 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2)
2439 RGE_MAC_CLRBIT(sc, 0xd42c, 0x0100);
2440 if (sc->rge_type != MAC_CFG3)
2441 RGE_PHY_CLRBIT(sc, 0xa466, 0x0001);
2442 RGE_PHY_CLRBIT(sc, 0xa468, 0x000a);
2447 rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val)
2451 RGE_WRITE_4(sc, RGE_CSIDR, val);
2452 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
2457 if (!(RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY))
2465 rge_read_csi(struct rge_softc *sc, uint32_t reg)
2469 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
2474 if (RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY)
2480 return (RGE_READ_4(sc, RGE_CSIDR));
2484 rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
2491 RGE_WRITE_4(sc, RGE_MACOCP, tmp);
2495 rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg)
2500 RGE_WRITE_4(sc, RGE_MACOCP, val);
2502 return (RGE_READ_4(sc, RGE_MACOCP) & RGE_MACOCP_DATA_MASK);
2506 rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)
2513 RGE_WRITE_4(sc, RGE_EPHYAR, tmp);
2517 if (!(RGE_READ_4(sc, RGE_EPHYAR) & RGE_EPHYAR_BUSY))
2525 rge_read_ephy(struct rge_softc *sc, uint16_t reg)
2531 RGE_WRITE_4(sc, RGE_EPHYAR, val);
2535 val = RGE_READ_4(sc, RGE_EPHYAR);
2546 rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val)
2557 rge_write_phy_ocp(sc, phyaddr, val);
2561 rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg)
2572 return (rge_read_phy_ocp(sc, phyaddr));
2576 rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
2583 RGE_WRITE_4(sc, RGE_PHYOCP, tmp);
2587 if (!(RGE_READ_4(sc, RGE_PHYOCP) & RGE_PHYOCP_BUSY))
2593 rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg)
2599 RGE_WRITE_4(sc, RGE_PHYOCP, val);
2603 val = RGE_READ_4(sc, RGE_PHYOCP);
2612 rge_get_link_status(struct rge_softc *sc)
2614 return ((RGE_READ_2(sc, RGE_PHYSTAT) & RGE_PHYSTAT_LINK) ? 1 : 0);
2620 struct rge_softc *sc = arg;
2622 RGE_WRITE_2(sc, RGE_TXSTART, RGE_TXSTART_START);
2628 struct rge_softc *sc = arg;
2632 rge_link_state(sc);
2635 timeout_add_sec(&sc->sc_timeout, 1);
2639 rge_link_state(struct rge_softc *sc)
2641 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
2644 if (rge_get_link_status(sc))
2657 struct rge_softc *sc = ifp->if_softc;
2660 if (!(RGE_READ_1(sc, RGE_CFG1) & RGE_CFG1_PM_EN)) {
2662 "cannot do WOL\n", sc->sc_dev.dv_xname);
2668 rge_iff(sc);
2671 RGE_MAC_SETBIT(sc, 0xc0b6, 0x0001);
2673 RGE_MAC_CLRBIT(sc, 0xc0b6, 0x0001);
2675 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2676 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE | RGE_CFG5_WOL_UCAST |
2678 RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_WOL_LINK | RGE_CFG3_WOL_MAGIC);
2680 RGE_SETBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE);
2681 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2687 rge_wol_power(struct rge_softc *sc)
2690 RGE_CLRBIT_1(sc, RGE_PPSW, 0x08);
2693 RGE_SETBIT_1(sc, RGE_CFG1, RGE_CFG1_PM_EN);
2694 RGE_SETBIT_1(sc, RGE_CFG2, RGE_CFG2_PMSTS_EN);
2762 struct rge_softc *sc = ks->ks_softc;
2770 command = RGE_READ_1(sc, RGE_CMD);
2777 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
2780 RGE_WRITE_4(sc, RGE_DTCCR_HI, cmd >> 32);
2781 bus_space_barrier(sc->rge_btag, sc->rge_bhandle, RGE_DTCCR_HI, 8,
2783 RGE_WRITE_4(sc, RGE_DTCCR_LO, cmd);
2784 bus_space_barrier(sc->rge_btag, sc->rge_bhandle, RGE_DTCCR_LO, 4,
2789 reg = RGE_READ_4(sc, RGE_DTCCR_LO);
2794 bus_space_barrier(sc->rge_btag, sc->rge_bhandle,
2798 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
2835 rge_kstat_attach(struct rge_softc *sc)
2843 sc->sc_dev.dv_xname);
2847 if (bus_dmamap_create(sc->sc_dmat,
2852 sc->sc_dev.dv_xname);
2856 if (bus_dmamem_alloc(sc->sc_dmat,
2861 sc->sc_dev.dv_xname);
2865 if (bus_dmamem_map(sc->sc_dmat,
2870 sc->sc_dev.dv_xname);
2874 if (bus_dmamap_load(sc->sc_dmat, rge_ks_sc->rge_ks_sc_map,
2878 sc->sc_dev.dv_xname);
2882 ks = kstat_create(sc->sc_dev.dv_xname, 0, "re-stats", 0,
2886 sc->sc_dev.dv_xname);
2894 ks->ks_softc = sc;
2901 sc->sc_kstat = ks;
2906 bus_dmamap_unload(sc->sc_dmat, rge_ks_sc->rge_ks_sc_map);
2908 bus_dmamem_unmap(sc->sc_dmat,
2911 bus_dmamem_free(sc->sc_dmat, &rge_ks_sc->rge_ks_sc_seg, 1);
2913 bus_dmamap_destroy(sc->sc_dmat, rge_ks_sc->rge_ks_sc_map);