Lines Matching defs:hw
248 struct ixgbe_hw *hw = &sc->hw;
285 error = ixgbe_init_shared_code(hw);
292 if (sc->hw.eeprom.ops.validate_checksum(&sc->hw, &csum) < 0) {
297 error = ixgbe_init_hw(hw);
310 bcopy(sc->hw.mac.addr, sc->arpcom.ac_enaddr,
321 if (sc->hw.mac.ops.enable_tx_laser)
322 sc->hw.mac.ops.enable_tx_laser(&sc->hw);
325 if (hw->phy.ops.set_phy_power)
326 hw->phy.ops.set_phy_power(&sc->hw, TRUE);
332 hw->mac.ops.get_bus_info(hw);
338 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT);
340 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext);
342 printf(", address %s\n", ether_sprintf(sc->hw.mac.addr));
378 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT);
380 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext);
402 struct ixgbe_hw *hw = &sc->hw;
411 ixgbe_init_hw(hw);
414 if (sc->hw.mac.ops.enable_tx_laser)
415 sc->hw.mac.ops.enable_tx_laser(&sc->hw);
418 if (hw->phy.ops.set_phy_power)
419 hw->phy.ops.set_phy_power(&sc->hw, TRUE);
422 hw->mac.ops.get_bus_info(hw);
425 ctrl_ext = IXGBE_READ_REG(&sc->hw, IXGBE_CTRL_EXT);
427 IXGBE_WRITE_REG(&sc->hw, IXGBE_CTRL_EXT, ctrl_ext);
511 IXGBE_WRITE_REG(&sc->hw, txr->tail, txr->next_avail_desc);
593 struct ixgbe_hw *hw = &sc->hw;
594 uint32_t swfw_mask = hw->phy.phy_semaphore_mask;
599 if (hw->phy.type == ixgbe_phy_fw)
602 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
606 if (hw->phy.ops.read_i2c_byte_unlocked(hw, 127,
610 hw->phy.ops.write_i2c_byte_unlocked(hw, 127,
616 if (hw->phy.ops.read_i2c_byte_unlocked(hw, i,
623 hw->phy.ops.write_i2c_byte_unlocked(hw, 127,
630 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
673 struct ixgbe_hw *hw = &sc->hw;
696 if (!(IXGBE_READ_REG(hw, IXGBE_TFCS) & IXGBE_TFCS_TXON)) {
706 printf("%s: Queue(%d) tdh = %d, hw tdt = %d\n", ifp->if_xname, i,
707 IXGBE_READ_REG(hw, IXGBE_TDH(i)),
708 IXGBE_READ_REG(hw, sc->tx_rings[i].tail));
722 * by the driver as a hw/sw initialization routine to get to a
745 ixgbe_set_rar(&sc->hw, 0, sc->hw.mac.addr, 0, IXGBE_RAH_AV);
748 bcopy(sc->arpcom.ac_enaddr, sc->hw.mac.addr,
750 ixgbe_set_rar(&sc->hw, 0, sc->hw.mac.addr, 0, 1);
751 sc->hw.addr_ctrl.rar_used_count = 1;
762 ixgbe_init_hw(&sc->hw);
787 mhadd = IXGBE_READ_REG(&sc->hw, IXGBE_MHADD);
790 IXGBE_WRITE_REG(&sc->hw, IXGBE_MHADD, mhadd);
794 txdctl = IXGBE_READ_REG(&sc->hw, IXGBE_TXDCTL(i));
804 IXGBE_WRITE_REG(&sc->hw, IXGBE_TXDCTL(i), txdctl);
808 rxdctl = IXGBE_READ_REG(&sc->hw, IXGBE_RXDCTL(i));
809 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
819 IXGBE_WRITE_REG(&sc->hw, IXGBE_RXDCTL(i), rxdctl);
821 if (IXGBE_READ_REG(&sc->hw, IXGBE_RXDCTL(i)) &
827 IXGBE_WRITE_FLUSH(&sc->hw);
828 IXGBE_WRITE_REG(&sc->hw, rxr[i].tail, rxr->last_desc_filled);
835 rxctrl = IXGBE_READ_REG(&sc->hw, IXGBE_RXCTRL);
836 if (sc->hw.mac.type == ixgbe_mac_82598EB)
839 sc->hw.mac.ops.enable_rx_dma(&sc->hw, rxctrl);
845 if (sc->hw.mac.type == ixgbe_mac_82598EB)
846 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
848 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
849 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
854 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
858 if (sc->hw.phy.type == ixgbe_phy_none) {
859 err = sc->hw.phy.ops.identify(&sc->hw);
869 if (sc->hw.mac.type != ixgbe_mac_82598EB)
871 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(0), itr);
875 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(sc->linkvec),
880 if (sc->hw.phy.ops.set_phy_power)
881 sc->hw.phy.ops.set_phy_power(&sc->hw, TRUE);
890 sc->hw.mac.ops.start_hw(&sc->hw);
911 struct ixgbe_hw *hw = &sc->hw;
914 gpie = IXGBE_READ_REG(&sc->hw, IXGBE_GPIE);
917 if (hw->device_id == IXGBE_DEV_ID_82598AT)
920 if (sc->hw.mac.type == ixgbe_mac_82599EB) {
925 if (hw->device_id != IXGBE_DEV_ID_82599_QSFP_SF_QP)
935 if (sc->hw.mac.type == ixgbe_mac_X540 ||
936 sc->hw.mac.type == ixgbe_mac_X550EM_x ||
937 sc->hw.mac.type == ixgbe_mac_X550EM_a) {
958 IXGBE_WRITE_REG(&sc->hw, IXGBE_GPIE, gpie);
967 struct ixgbe_hw *hw = &sc->hw;
973 switch (hw->mac.type) {
985 rxpb = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) >> 10;
986 hw->fc.high_water[0] = rxpb - size;
989 switch (hw->mac.type) {
1000 hw->fc.low_water[0] = IXGBE_BT2KB(tmp);
1002 hw->fc.requested_mode = sc->fc;
1003 hw->fc.pause_time = IXGBE_FC_PAUSE;
1004 hw->fc.send_xon = TRUE;
1016 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
1018 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS, mask);
1022 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS_EX(0), mask);
1025 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMS_EX(1), mask);
1045 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
1047 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, mask);
1051 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(0), mask);
1054 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(1), mask);
1123 struct ixgbe_hw *hw = &sc->hw;
1128 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_OTHER);
1130 reg_eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1134 IXGBE_WRITE_REG(hw, IXGBE_EICR, reg_eicr);
1136 reg_eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1146 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1152 if (hw->mac.type != ixgbe_mac_82598EB) {
1156 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
1162 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_TS);
1167 if (ixgbe_is_sfp(hw)) {
1168 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) {
1171 } else if (hw->mac.type == ixgbe_mac_X540 ||
1172 hw->mac.type == ixgbe_mac_X550 ||
1173 hw->mac.type == ixgbe_mac_X550EM_x) {
1182 IXGBE_WRITE_REG(hw, IXGBE_EICR, mod_mask);
1186 } else if ((hw->phy.media_type != ixgbe_media_type_copper) &&
1189 IXGBE_WRITE_REG(hw, IXGBE_EICR, msf_mask);
1197 if ((hw->device_id == IXGBE_DEV_ID_82598AT) &&
1201 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1205 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T &&
1208 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0_X540);
1214 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1328 switch (sc->hw.fc.current_mode) {
1358 struct ixgbe_hw *hw = &sc->hw;
1365 if (hw->phy.media_type == ixgbe_media_type_backplane)
1407 hw->mac.autotry_restart = TRUE;
1408 hw->mac.ops.setup_link(hw, speed, TRUE);
1526 fctrl = IXGBE_READ_REG(&sc->hw, IXGBE_FCTRL);
1548 sc->hw.mac.ops.update_mc_addr_list(&sc->hw, update_ptr, mcnt,
1552 IXGBE_WRITE_REG(&sc->hw, IXGBE_FCTRL, fctrl);
1561 ixgbe_mc_array_itr(struct ixgbe_hw *hw, uint8_t **update_ptr, uint32_t *vmdq)
1581 ixgbe_check_link(&sc->hw, &sc->link_speed, &sc->link_up, 0);
1603 sc->hw.mac.ops.fc_enable(&sc->hw);
1637 sc->hw.mac.ops.reset_hw(&sc->hw);
1638 sc->hw.adapter_stopped = FALSE;
1639 sc->hw.mac.ops.stop_adapter(&sc->hw);
1640 if (sc->hw.mac.type == ixgbe_mac_82599EB)
1641 sc->hw.mac.ops.stop_mac_link_on_d3(&sc->hw);
1643 if (sc->hw.mac.ops.disable_tx_laser)
1644 sc->hw.mac.ops.disable_tx_laser(&sc->hw);
1647 ixgbe_set_rar(&sc->hw, 0, sc->hw.mac.addr, 0, IXGBE_RAH_AV);
1683 sc->hw.vendor_id = PCI_VENDOR(pa->pa_id);
1684 sc->hw.device_id = PCI_PRODUCT(pa->pa_id);
1687 sc->hw.revision_id = PCI_REVISION(reg);
1690 sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
1691 sc->hw.subsystem_device_id = PCI_PRODUCT(reg);
1694 ixgbe_set_mac_type(&sc->hw);
1697 if (sc->hw.mac.type != ixgbe_mac_82598EB)
1698 sc->hw.phy.smart_speed = ixgbe_smart_speed;
1835 maxq = (sc->hw.mac.type == ixgbe_mac_82598EB) ? 8 : 16;
1859 sc->hw.hw_addr = (uint8_t *)os->os_membase;
1863 sc->hw.back = os;
1928 if (sc->hw.mac.type != ixgbe_mac_82598EB) {
1973 struct ixgbe_hw *hw = &sc->hw;
1976 sc->phy_layer = hw->mac.ops.get_supported_physical_layer(hw);
1990 if (hw->phy.multispeed_fiber)
1996 if (hw->phy.multispeed_fiber)
2012 if (hw->device_id == IXGBE_DEV_ID_82598AT) {
2027 if (ixgbe_is_sfp(&sc->hw)) {
2028 if (sc->hw.phy.multispeed_fiber) {
2029 sc->hw.mac.ops.setup_sfp(&sc->hw);
2030 if (sc->hw.mac.ops.enable_tx_laser)
2031 sc->hw.mac.ops.enable_tx_laser(&sc->hw);
2036 if (sc->hw.mac.ops.check_link)
2037 err = sc->hw.mac.ops.check_link(&sc->hw, &autoneg,
2041 autoneg = sc->hw.phy.autoneg_advertised;
2042 if ((!autoneg) && (sc->hw.mac.ops.get_link_capabilities))
2043 err = sc->hw.mac.ops.get_link_capabilities(&sc->hw,
2047 if (sc->hw.mac.ops.setup_link)
2048 sc->hw.mac.ops.setup_link(&sc->hw,
2348 struct ixgbe_hw *hw = &sc->hw;
2361 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(i),
2363 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(i), (tdba >> 32));
2364 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(i),
2371 IXGBE_WRITE_REG(hw, IXGBE_TDH(i), 0);
2372 IXGBE_WRITE_REG(hw, txr->tail, 0);
2380 switch (hw->mac.type) {
2382 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
2387 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
2391 switch (hw->mac.type) {
2393 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), txctrl);
2398 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), txctrl);
2404 if (hw->mac.type != ixgbe_mac_82598EB) {
2406 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2408 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2410 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2412 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2413 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2415 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2419 hlreg = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2421 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg);
2849 IXGBE_WRITE_REG(&sc->hw, rxr->tail, rxr->last_desc_filled);
2888 struct ixgbe_hw *hw = &sc->hw;
2897 ixgbe_disable_rx(hw);
2900 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2902 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
2906 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2908 hlreg = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2913 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg);
2916 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2925 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2934 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i),
2936 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(i), (rdba >> 32));
2937 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(i),
2942 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(i), srrctl);
2948 rdrxctl = IXGBE_READ_REG(&sc->hw, IXGBE_RSCCTL(i));
2954 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(i), rdrxctl);
2958 IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
2959 IXGBE_WRITE_REG(hw, rxr->tail, 0);
2962 if (sc->hw.mac.type != ixgbe_mac_82598EB) {
2967 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2970 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2988 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2994 struct ixgbe_hw *hw = &sc->hw;
3004 switch (sc->hw.mac.type) {
3029 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3031 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3039 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), rss_key[i]);
3054 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3390 IXGBE_WRITE_REG(&sc->hw, IXGBE_VFTA(i),
3394 ctrl = IXGBE_READ_REG(&sc->hw, IXGBE_VLNCTRL);
3402 if (sc->hw.mac.type == ixgbe_mac_82598EB)
3404 IXGBE_WRITE_REG(&sc->hw, IXGBE_VLNCTRL, ctrl);
3407 if (sc->hw.mac.type != ixgbe_mac_82598EB) {
3409 ctrl = IXGBE_READ_REG(&sc->hw, IXGBE_RXDCTL(i));
3411 IXGBE_WRITE_REG(&sc->hw, IXGBE_RXDCTL(i), ctrl);
3419 struct ixgbe_hw *hw = &sc->hw;
3424 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3427 switch (sc->hw.mac.type) {
3439 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
3450 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
3451 hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T)
3457 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
3465 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
3468 IXGBE_WRITE_FLUSH(hw);
3475 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIAC, 0);
3476 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
3477 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, ~0);
3479 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC, 0xFFFF0000);
3480 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(0), ~0);
3481 IXGBE_WRITE_REG(&sc->hw, IXGBE_EIMC_EX(1), ~0);
3483 IXGBE_WRITE_FLUSH(&sc->hw);
3487 ixgbe_read_pci_cfg(struct ixgbe_hw *hw, uint32_t reg)
3497 pa = &((struct ixgbe_osdep *)hw->back)->os_pa;
3507 ixgbe_write_pci_cfg(struct ixgbe_hw *hw, uint32_t reg, uint16_t value)
3518 pa = &((struct ixgbe_osdep *)hw->back)->os_pa;
3537 struct ixgbe_hw *hw = &sc->hw;
3542 switch (hw->mac.type) {
3550 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
3553 IXGBE_WRITE_REG(&sc->hw, IXGBE_IVAR(index), ivar);
3563 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
3566 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
3569 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
3572 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
3595 IXGBE_WRITE_REG(&sc->hw,
3609 struct ixgbe_hw *hw = &sc->hw;
3612 err = hw->phy.ops.identify_sfp(hw);
3618 err = hw->mac.ops.setup_sfp(hw);
3635 struct ixgbe_hw *hw = &sc->hw;
3639 autoneg = hw->phy.autoneg_advertised;
3640 if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) {
3641 if (hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiate))
3644 if (hw->mac.ops.setup_link)
3645 hw->mac.ops.setup_link(hw, autoneg, TRUE);
3658 struct ixgbe_hw *hw = &sc->hw;
3661 error = hw->phy.ops.handle_lasi(hw);
3925 ix_read36(struct ixgbe_hw *hw, bus_size_t loreg, bus_size_t hireg)
3929 lo = IXGBE_READ_REG(hw, loreg);
3930 hi = IXGBE_READ_REG(hw, hireg);
3940 struct ixgbe_hw *hw = &sc->hw;
3952 if (sc->hw.mac.type == ixgbe_mac_82598EB)
3953 v = IXGBE_READ_REG(hw, reg + 4);
3955 v = ix_read36(hw, reg, reg + 4);
3957 v = IXGBE_READ_REG(hw, reg);
3963 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
3965 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3967 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3970 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3972 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3986 struct ixgbe_hw *hw = &sc->hw;
3989 kstat_kv_u64(&stats->qprc) += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3990 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
3992 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3994 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
3997 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3999 ix_read36(hw, IXGBE_QBRC_L(i), IXGBE_QBRC_H(i));
4013 struct ixgbe_hw *hw = &sc->hw;
4016 kstat_kv_u64(&stats->qptc) += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4017 if (sc->hw.mac.type == ixgbe_mac_82598EB) {
4019 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4022 ix_read36(hw, IXGBE_QBTC_L(i), IXGBE_QBTC_H(i));
4053 IXGBE_WRITE_REG(&sc->hw, IXGBE_RQSMR(i), r);
4054 IXGBE_WRITE_REG(&sc->hw, IXGBE_TQSM(i), r);