Lines Matching defs:qid
1413 iwm_alloc_tx_ring(struct iwm_softc *sc, struct iwm_tx_ring *ring, int qid)
1419 ring->qid = qid;
1453 if (qid > IWM_LAST_AGG_TX_QUEUE)
1475 if (qid == IWM_CMD_QUEUE || qid == IWM_DQA_CMD_QUEUE)
1516 sc->qfullmsk &= ~(1 << ring->qid);
1517 sc->qenablemsk &= ~(1 << ring->qid);
1519 if (ring->qid == sc->cmdqid && ring->queued > 0) {
2069 int qid;
2098 for (qid = 0; qid < nitems(sc->txq); qid++)
2099 iwm_reset_tx_ring(sc, &sc->txq[qid]);
2310 int qid, err;
2321 for (qid = 0; qid < nitems(sc->txq); qid++) {
2322 struct iwm_tx_ring *txq = &sc->txq[qid];
2325 IWM_WRITE(sc, IWM_FH_MEM_CBBC_QUEUE(qid),
2385 iwm_enable_ac_txq(struct iwm_softc *sc, int qid, int fifo)
2390 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | 0);
2392 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid),
2396 err = iwm_clear_bits_prph(sc, IWM_SCD_AGGR_SEL, (1 << qid));
2401 iwm_write_prph(sc, IWM_SCD_QUEUE_RDPTR(qid), 0);
2404 sc->sched_base + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid), 0);
2408 sc->sched_base + IWM_SCD_CONTEXT_QUEUE_OFFSET(qid) +
2416 iwm_write_prph(sc, IWM_SCD_QUEUE_STATUS_BITS(qid),
2422 if (qid == sc->cmdqid)
2424 iwm_read_prph(sc, IWM_SCD_EN_CTRL) | (1 << qid));
2430 iwm_enable_txq(struct iwm_softc *sc, int sta_id, int qid, int fifo,
2433 struct iwm_tx_ring *ring = &sc->txq[qid];
2453 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | idx);
2459 cmd.scd_queue = qid;
2472 sc->qenablemsk |= (1 << qid);
2477 iwm_disable_txq(struct iwm_softc *sc, int sta_id, int qid, uint8_t tid)
2484 cmd.scd_queue = qid;
2492 sc->qenablemsk &= ~(1 << qid);
3551 int qid = IWM_FIRST_AGG_TX_QUEUE + tid;
3560 if (tid >= IWM_MAX_TID_COUNT || qid > IWM_LAST_AGG_TX_QUEUE)
3564 if ((sc->tx_ba_queue_mask & (1 << qid)) != 0)
3567 if ((sc->tx_ba_queue_mask & (1 << qid)) == 0)
3571 ring = &sc->txq[qid];
3585 in->tfd_queue_msk |= (1 << qid);
3602 if (start && (sc->qenablemsk & (1 << qid)) == 0) {
3609 err = iwm_enable_txq(sc, IWM_STATION_ID, qid, fifo, 1, tid,
3614 DEVNAME(sc), qid, err);
3651 sc->tx_ba_queue_mask |= (1 << qid);
3654 sc->tx_ba_queue_mask &= ~(1 << qid);
3768 int qid = IWM_FIRST_AGG_TX_QUEUE + tid;
3783 if ((sc->tx_ba_queue_mask & (1 << qid)) != 0)
3801 int qid = IWM_FIRST_AGG_TX_QUEUE + tid;
3807 if ((sc->tx_ba_queue_mask & (1 << qid)) == 0)
5703 iwm_reset_sched(sc, ring->qid, ring->tail, IWM_STATION_ID);
5720 int tid = cmd_hdr->qid - IWM_FIRST_AGG_TX_QUEUE;
5738 uint8_t qid = agg_status[i].qid;
5746 if (qid != cmd_hdr->qid)
5842 int qid = cmd_hdr->qid;
5843 struct iwm_tx_ring *ring = &sc->txq[qid];
5855 if (qid < IWM_FIRST_AGG_TX_QUEUE && tx_resp->frame_count > 1)
5857 if (qid > IWM_LAST_AGG_TX_QUEUE)
5863 sc->sc_tx_timer[qid] = 0;
5871 if (qid >= IWM_FIRST_AGG_TX_QUEUE) {
5895 sc->qfullmsk &= ~(1 << ring->qid);
5958 int qid;
5970 qid = le16toh(ban->scd_flow);
5971 if (qid < IWM_FIRST_AGG_TX_QUEUE || qid > IWM_LAST_AGG_TX_QUEUE)
5975 if (qid != IWM_FIRST_AGG_TX_QUEUE + ban->tid)
5978 sc->sc_tx_timer[qid] = 0;
5984 ring = &sc->txq[qid];
6363 cmd->hdr_wide.qid = ring->qid;
6371 cmd->hdr.qid = ring->qid;
6415 iwm_update_sched(sc, ring->qid, ring->cur, 0, 0);
6420 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
6514 iwm_cmd_done(struct iwm_softc *sc, int qid, int idx, int code)
6519 if (qid != sc->cmdqid) {
6548 iwm_update_sched(struct iwm_softc *sc, int qid, int idx, uint8_t sta_id,
6566 scd_bc_tbl[qid].tfd_offset[idx] = val;
6568 scd_bc_tbl[qid].tfd_offset[IWM_TFD_QUEUE_SIZE_MAX + idx] = val;
6574 iwm_reset_sched(struct iwm_softc *sc, int qid, int idx, uint8_t sta_id)
6587 scd_bc_tbl[qid].tfd_offset[idx] = val;
6589 scd_bc_tbl[qid].tfd_offset[IWM_TFD_QUEUE_SIZE_MAX + idx] = val;
6720 int qid, hasqos;
6746 qid = IWM_DQA_INJECT_MONITOR_QUEUE;
6748 qid = IWM_AUX_QUEUE;
6750 qid = IWM_DQA_MIN_MGMT_QUEUE + ac;
6752 qid = ac;
6767 qid = agg_qid;
6773 ring = &sc->txq[qid];
6781 cmd->hdr.qid = ring->qid;
6985 iwm_update_sched(sc, ring->qid, ring->cur, tx->sta_id, totlen);
6989 IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
6993 sc->qfullmsk |= 1 << ring->qid;
6997 sc->sc_tx_timer[ring->qid] = 15;
7249 int qid;
7252 qid = IWM_DQA_INJECT_MONITOR_QUEUE;
7254 qid = IWM_AUX_QUEUE;
7255 in->tfd_queue_msk |= (1 << qid);
7259 int qid = ac;
7262 qid += IWM_DQA_MIN_MGMT_QUEUE;
7263 in->tfd_queue_msk |= (1 << qid);
7374 int err, qid;
7379 qid = IWM_DQA_AUX_QUEUE;
7380 err = iwm_enable_txq(sc, IWM_AUX_STA_ID, qid,
7383 qid = IWM_AUX_QUEUE;
7384 err = iwm_enable_ac_txq(sc, qid, IWM_TX_FIFO_MCAST);
7395 cmd.tfd_queue_msk = htole32(1 << qid);
8602 int qid = IWM_FIRST_AGG_TX_QUEUE + tid;
8604 if ((sc->tx_ba_queue_mask & (1 << qid)) == 0)
8610 err = iwm_disable_txq(sc, IWM_STATION_ID, qid, tid);
8613 in->tfd_queue_msk &= ~(1 << qid);
9054 int qid = IWM_FIRST_AGG_TX_QUEUE + tid;
9055 if ((sc->tx_ba_queue_mask & (1 << qid)) == 0)
9060 err = iwm_disable_txq(sc, IWM_STATION_ID, qid, tid);
9063 in->tfd_queue_msk &= ~(1 << qid);
10162 int err, i, ac, qid, s;
10301 qid = IWM_DQA_INJECT_MONITOR_QUEUE;
10303 qid = IWM_AUX_QUEUE;
10304 err = iwm_enable_txq(sc, IWM_MONITOR_STA_ID, qid,
10315 qid = ac + IWM_DQA_MIN_MGMT_QUEUE;
10317 qid = ac;
10318 err = iwm_enable_txq(sc, IWM_STATION_ID, qid,
10922 printf(" tx ring %2d: qid=%-2d cur=%-3d "
10924 i, ring->qid, ring->cur, ring->queued);
10950 int qid, idx, code;
10952 qid = pkt->hdr.qid & ~0x80;
10956 return (!(qid == 0 && idx == 0 && code == 0) &&
10968 int qid, idx, code, handled = 1;
10976 qid = pkt->hdr.qid;
11299 (qid & ~0x80), idx);
11310 if (handled && !(qid & (1 << 7))) {
11311 iwm_cmd_done(sc, qid, idx, code);