Lines Matching defs:hw
197 struct igc_hw *hw = &sc->hw;
218 if (igc_setup_init_funcs(hw, true)) {
223 hw->mac.autoneg = DO_AUTO_NEG;
224 hw->phy.autoneg_wait_to_complete = false;
225 hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
228 if (hw->phy.media_type == igc_media_type_copper)
229 hw->phy.mdix = AUTO_ALL_MODES;
232 sc->hw.mac.max_frame_size = 9234;
243 if (igc_check_reset_block(hw))
247 sc->hw.dev_spec._i225.eee_disable = true;
249 igc_reset_hw(hw);
252 if (igc_validate_nvm_checksum(hw) < 0) {
258 if (igc_validate_nvm_checksum(hw) < 0) {
265 if (igc_read_mac_addr(hw) < 0) {
270 if (!igc_is_valid_ether_addr(hw->mac.addr)) {
275 memcpy(sc->sc_ac.ac_enaddr, sc->hw.mac.addr, ETHER_ADDR_LEN);
284 hw->mac.get_link_status = true;
290 printf(", address %s\n", ether_sprintf(sc->hw.mac.addr));
321 igc_phy_hw_reset(&sc->hw);
343 sc->hw.device_id = PCI_PRODUCT(pa->pa_id);
346 if (igc_set_mac_type(&sc->hw)) {
365 sc->hw.hw_addr = (uint8_t *)os->os_membase;
366 sc->hw.back = os;
502 struct igc_hw *hw = &sc->hw;
531 hw->fc.high_water = rx_buffer_size -
532 roundup2(sc->hw.mac.max_frame_size, 1024);
534 hw->fc.low_water = hw->fc.high_water - 16;
537 hw->fc.requested_mode = sc->fc;
539 hw->fc.requested_mode = igc_fc_full;
541 hw->fc.pause_time = IGC_FC_PAUSE_TIME;
543 hw->fc.send_xon = true;
546 igc_reset_hw(hw);
547 IGC_WRITE_REG(hw, IGC_WUC, 0);
550 if (igc_init_hw(hw) < 0) {
558 IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN);
559 igc_get_phy_info(hw);
560 igc_check_for_link(hw);
571 struct igc_hw *hw = &sc->hw;
576 max_frame_size = sc->hw.mac.max_frame_size;
579 IGC_WRITE_REG(hw, IGC_DMACR, reg);
585 IGC_WRITE_REG(hw, IGC_DMCTXTH, 0);
590 reg = IGC_READ_REG(hw, IGC_FCRTC);
594 IGC_WRITE_REG(hw, IGC_FCRTC, reg);
599 reg = IGC_READ_REG(hw, IGC_DMACR);
613 status = IGC_READ_REG(hw, IGC_STATUS);
620 IGC_WRITE_REG(hw, IGC_DMACR, reg);
622 IGC_WRITE_REG(hw, IGC_DMCRTRH, 0);
625 reg = IGC_READ_REG(hw, IGC_DMCTLX);
632 status = IGC_READ_REG(hw, IGC_STATUS);
639 IGC_WRITE_REG(hw, IGC_DMCTLX, reg);
642 IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE -
646 reg = IGC_READ_REG(hw, IGC_PCIEMISC);
648 IGC_WRITE_REG(hw, IGC_PCIEMISC, reg);
802 ifp->if_hardmtu = sc->hw.mac.max_frame_size - ETHER_HDR_LEN -
863 bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac.addr, ETHER_ADDR_LEN);
866 igc_rar_set(&sc->hw, sc->hw.mac.addr, 0);
873 IGC_WRITE_REG(&sc->hw, IGC_VET, ETHERTYPE_VLAN);
896 ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL);
898 IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl);
904 igc_clear_hw_cntrs_base_generic(&sc->hw);
909 IGC_READ_REG(&sc->hw, IGC_ICR);
910 IGC_WRITE_REG(&sc->hw, IGC_ICS, IGC_ICS_LSC);
916 igc_set_eee_i225(&sc->hw, true, true, true);
927 IGC_WRITE_REG(&sc->hw, IGC_RDT(i),
1066 IGC_WRITE_REG(&sc->hw, IGC_TDT(txr->me), prod);
1145 igc_reset_hw(&sc->hw);
1146 IGC_WRITE_REG(&sc->hw, IGC_WUC, 0);
1285 IGC_WRITE_REG(&sc->hw, IGC_RDT(rxr->me),
1513 switch (sc->hw.fc.current_mode) {
1548 sc->hw.mac.autoneg = DO_AUTO_NEG;
1552 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1555 sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL;
1558 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1562 sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL;
1564 sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF;
1568 sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL;
1570 sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF;
1596 reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL);
1616 igc_update_mc_addr_list(&sc->hw, mta, mcnt);
1619 IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl);
1626 struct igc_hw *hw = &sc->hw;
1629 if (hw->mac.get_link_status == true)
1630 igc_check_for_link(hw);
1632 if (IGC_READ_REG(&sc->hw, IGC_STATUS) & IGC_STATUS_LU) {
1634 igc_get_speed_and_duplex(hw, &sc->link_speed,
1702 struct igc_hw *hw = &sc->hw;
1708 IGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME |
1723 IGC_WRITE_REG(hw, IGC_EITR(iq->msix), newitr);
1729 IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar);
1735 struct igc_hw *hw = &sc->hw;
1739 ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index);
1757 IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar);
1763 IGC_WRITE_REG(&sc->hw, IGC_EIMS, eims);
1769 struct igc_hw *hw = &sc->hw;
1773 IGC_WRITE_REG(hw, IGC_EIAC, mask);
1774 IGC_WRITE_REG(hw, IGC_EIAM, mask);
1775 IGC_WRITE_REG(hw, IGC_EIMS, mask);
1776 IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC);
1777 IGC_WRITE_FLUSH(hw);
1783 struct igc_hw *hw = &sc->hw;
1785 IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff);
1786 IGC_WRITE_REG(hw, IGC_EIAC, 0);
1787 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
1788 IGC_WRITE_FLUSH(hw);
1795 uint32_t reg_icr = IGC_READ_REG(&sc->hw, IGC_ICR);
1799 sc->hw.mac.get_link_status = true;
1804 IGC_WRITE_REG(&sc->hw, IGC_IMS, IGC_IMS_LSC);
1805 IGC_WRITE_REG(&sc->hw, IGC_EIMS, sc->msix_linkmask);
1932 struct igc_hw *hw = &sc->hw;
1944 IGC_WRITE_REG(hw, IGC_TDLEN(i),
1946 IGC_WRITE_REG(hw, IGC_TDBAH(i), (uint32_t)(bus_addr >> 32));
1947 IGC_WRITE_REG(hw, IGC_TDBAL(i), (uint32_t)bus_addr);
1950 IGC_WRITE_REG(hw, IGC_TDT(i), 0);
1951 IGC_WRITE_REG(hw, IGC_TDH(i), 0);
1963 IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl);
1968 tctl = IGC_READ_REG(&sc->hw, IGC_TCTL);
1974 IGC_WRITE_REG(&sc->hw, IGC_TCTL, tctl);
2244 struct igc_hw *hw = &sc->hw;
2252 rctl = IGC_READ_REG(hw, IGC_RCTL);
2253 IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN);
2258 IGC_RCTL_RDMTS_HALF | (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT);
2264 if (sc->hw.mac.max_frame_size != ETHER_MAX_LEN)
2274 IGC_WRITE_REG(hw, IGC_ITR, DEFAULT_ITR);
2276 rxcsum = IGC_READ_REG(hw, IGC_RXCSUM);
2282 IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum);
2306 IGC_WRITE_REG(hw, IGC_RXDCTL(i), 0);
2312 IGC_WRITE_REG(hw, IGC_RDLEN(i),
2314 IGC_WRITE_REG(hw, IGC_RDBAH(i), (uint32_t)(bus_addr >> 32));
2315 IGC_WRITE_REG(hw, IGC_RDBAL(i), (uint32_t)bus_addr);
2316 IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl);
2319 IGC_WRITE_REG(hw, IGC_RDH(i), 0);
2320 IGC_WRITE_REG(hw, IGC_RDT(i), 0);
2323 rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i));
2329 IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl);
2336 IGC_WRITE_REG(hw, IGC_RCTL, rctl);
2397 struct igc_hw *hw = &sc->hw;
2428 IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta);
2444 IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i]);
2453 IGC_WRITE_REG(hw, IGC_MRQC, mrqc);
2467 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT);
2468 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
2482 ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT);
2483 IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
2708 struct igc_hw *hw = &sc->hw;
2719 kstat_kv_u64(&kvs[i]) += IGC_READ_REG(hw, c->reg);
2722 lo = IGC_READ_REG(hw, IGC_GORCL);
2723 hi = IGC_READ_REG(hw, IGC_GORCH);
2727 lo = IGC_READ_REG(hw, IGC_GOTCL);
2728 hi = IGC_READ_REG(hw, IGC_GOTCH);
2732 lo = IGC_READ_REG(hw, IGC_TORL);
2733 hi = IGC_READ_REG(hw, IGC_TORH);
2737 lo = IGC_READ_REG(hw, IGC_TOTL);
2738 hi = IGC_READ_REG(hw, IGC_TOTH);
2742 lo = IGC_READ_REG(hw, IGC_HGORCL);
2743 hi = IGC_READ_REG(hw, IGC_HGORCH);
2747 lo = IGC_READ_REG(hw, IGC_HGOTCL);
2748 hi = IGC_READ_REG(hw, IGC_HGOTCH);