Lines Matching defs:ret_val
744 int32_t ret_val = E1000_ERR_CONFIG;
758 ret_val = em_read_sfp_data_byte(hw,
761 if (ret_val == E1000_SUCCESS)
766 if (ret_val != E1000_SUCCESS)
769 ret_val = em_read_sfp_data_byte(hw,
772 if (ret_val != E1000_SUCCESS)
788 ret_val = E1000_ERR_CONFIG;
792 ret_val = E1000_ERR_CONFIG;
795 ret_val = E1000_SUCCESS;
799 return ret_val;
935 int32_t ret_val;
958 ret_val = em_set_pciex_completion_timeout(hw);
959 if (ret_val) {
1098 ret_val = em_hv_phy_workarounds_ich8lan(hw);
1099 if (ret_val)
1100 return ret_val;
1103 ret_val = em_lv_phy_workarounds_ich8lan(hw);
1104 if (ret_val)
1105 return ret_val;
1147 ret_val = em_get_auto_rd_done(hw);
1148 if (ret_val)
1149 return ret_val;
1425 int ret_val = E1000_SUCCESS;
1449 ret_val = -E1000_ERR_PHY;
1471 ret_val = em_get_software_flag(hw);
1472 if (ret_val)
1480 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg);
1481 if (ret_val) {
1491 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg);
1492 if (ret_val)
1506 ret_val = em_read_phy_reg(hw, HV_PM_CTRL, &phy_reg);
1507 if (ret_val)
1513 ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1, &phy_reg);
1514 if (ret_val)
1542 if (ret_val)
1543 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1545 return ret_val;
1566 int32_t ret_val;
1630 ret_val = em_set_mdio_slow_mode_hv(hw);
1631 if (ret_val)
1632 return ret_val;
1636 ret_val = em_id_led_init(hw);
1637 if (ret_val) {
1639 return ret_val;
1750 ret_val = em_phy_reset(hw);
1751 if (ret_val)
1752 return ret_val;
1756 ret_val = em_setup_link(hw);
1867 return ret_val;
1879 int32_t ret_val;
1894 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1895 if (ret_val) {
1896 return ret_val;
1901 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
1903 if (ret_val)
1904 return ret_val;
1924 int32_t ret_val;
1965 ret_val = em_read_eeprom(hw,
1967 if (ret_val) {
2004 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
2006 if (ret_val) {
2015 ret_val = em_detect_gig_phy(hw);
2016 if (ret_val) {
2021 return ret_val;
2029 ret_val = em_setup_copper_link(hw);
2032 ret_val = em_setup_fiber_serdes_link(hw);
2089 return ret_val;
2133 int32_t ret_val;
2165 ret_val = em_adjust_serdes_amplitude(hw);
2166 if (ret_val)
2167 return ret_val;
2201 ret_val = em_set_vco_speed(hw);
2202 if (ret_val)
2203 return ret_val;
2305 ret_val = em_check_for_link(hw);
2306 if (ret_val) {
2308 return ret_val;
2330 int32_t ret_val;
2349 ret_val = em_phy_hw_reset(hw);
2350 if (ret_val)
2351 return ret_val;
2355 ret_val = em_set_phy_mode(hw);
2356 if (ret_val)
2357 return ret_val;
2361 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2364 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2398 int32_t ret_val;
2405 ret_val = em_phy_reset(hw);
2406 if (ret_val) {
2408 return ret_val;
2424 ret_val = em_set_d3_lplu_state(hw, FALSE);
2425 if (ret_val) {
2427 return ret_val;
2438 ret_val = em_set_lplu_state_pchlan(hw, FALSE);
2440 ret_val = em_set_d0_lplu_state(hw, FALSE);
2441 if (ret_val) {
2443 return ret_val;
2446 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2447 if (ret_val)
2448 return ret_val;
2474 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2475 if (ret_val)
2476 return ret_val;
2493 ret_val = em_read_phy_reg(hw,
2495 if (ret_val)
2496 return ret_val;
2499 ret_val = em_write_phy_reg(hw,
2501 if (ret_val)
2502 return ret_val;
2504 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
2506 if (ret_val)
2507 return ret_val;
2510 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
2512 if (ret_val)
2513 return ret_val;
2515 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2516 if (ret_val)
2517 return ret_val;
2538 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2539 if (ret_val)
2540 return ret_val;
2553 int32_t ret_val;
2561 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
2563 if (ret_val)
2564 return ret_val;
2570 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
2572 if (ret_val)
2573 return ret_val;
2579 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL,
2582 if (ret_val)
2583 return ret_val;
2607 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL,
2610 if (ret_val)
2611 return ret_val;
2614 ret_val = em_phy_reset(hw);
2615 if (ret_val) {
2617 return ret_val;
2622 ret_val = em_write_kmrn_reg(hw,
2626 if (ret_val)
2627 return ret_val;
2629 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2,
2631 if (ret_val)
2632 return ret_val;
2635 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2,
2638 if (ret_val)
2639 return ret_val;
2645 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
2647 if (ret_val)
2648 return ret_val;
2657 ret_val = em_write_phy_reg(hw,
2659 if (ret_val)
2660 return ret_val;
2662 ret_val = em_read_phy_reg(hw,
2664 if (ret_val)
2665 return ret_val;
2668 ret_val = em_write_phy_reg(hw,
2671 if (ret_val)
2672 return ret_val;
2678 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
2680 if (ret_val)
2681 return ret_val;
2683 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
2685 if (ret_val)
2686 return ret_val;
2699 int32_t ret_val;
2714 ret_val = em_set_lplu_state_pchlan(hw, FALSE);
2717 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2718 if (ret_val)
2719 return ret_val;
2723 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2725 if (ret_val)
2726 return ret_val;
2728 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2730 if (ret_val)
2731 return ret_val;
2773 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2774 if (ret_val)
2775 return ret_val;
2785 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2787 if (ret_val)
2788 return ret_val;
2801 ret_val = em_write_phy_reg(hw,
2803 if (ret_val)
2804 return ret_val;
2811 ret_val = em_write_phy_reg(hw,
2813 if (ret_val)
2814 return ret_val;
2823 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003);
2824 if (ret_val)
2825 return ret_val;
2828 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000);
2829 if (ret_val)
2830 return ret_val;
2833 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2835 if (ret_val)
2836 return ret_val;
2841 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
2843 if (ret_val)
2844 return ret_val;
2847 ret_val = em_phy_reset(hw);
2848 if (ret_val) {
2850 return ret_val;
2863 int32_t ret_val;
2872 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data);
2873 if (ret_val)
2874 return ret_val;
2879 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data);
2880 if (ret_val)
2881 return ret_val;
2888 ret_val = em_set_lplu_state_pchlan(hw, FALSE);
2889 if (ret_val) {
2891 return ret_val;
2902 int32_t ret_val;
2908 ret_val = em_phy_reset(hw);
2909 if (ret_val)
2913 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data);
2914 if (ret_val)
2920 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data);
2923 return ret_val;
2929 int32_t ret_val;
2943 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
2944 if (ret_val) {
2946 return ret_val;
2952 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
2953 if (ret_val) {
2955 return ret_val;
2959 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data);
2960 if (ret_val) {
2962 return ret_val;
2966 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data);
2967 if (ret_val) {
2969 return ret_val;
2973 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data);
2974 if (ret_val) {
2976 return ret_val;
2980 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data);
2981 if (ret_val) {
2983 return ret_val;
2987 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data);
2988 if (ret_val) {
2990 return ret_val;
2995 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data);
2996 if (ret_val) {
2998 return ret_val;
3002 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data);
3003 if (ret_val) {
3005 return ret_val;
3012 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data);
3013 if (ret_val) {
3015 return ret_val;
3020 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data);
3021 if (ret_val) {
3023 return ret_val;
3026 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data);
3027 if (ret_val) {
3029 return ret_val;
3036 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data);
3037 if (ret_val) {
3039 return ret_val;
3046 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data);
3047 if (ret_val) {
3049 return ret_val;
3063 int32_t ret_val;
3083 ret_val = em_phy_setup_autoneg(hw);
3084 if (ret_val) {
3086 return ret_val;
3093 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
3094 if (ret_val)
3095 return ret_val;
3098 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
3099 if (ret_val)
3100 return ret_val;
3106 ret_val = em_wait_autoneg(hw);
3107 if (ret_val) {
3110 return ret_val;
3133 int32_t ret_val;
3140 ret_val = em_config_mac_to_phy(hw);
3141 if (ret_val) {
3143 return ret_val;
3146 ret_val = em_config_fc_after_link_up(hw);
3147 if (ret_val) {
3149 return ret_val;
3153 ret_val = em_config_dsp_after_link_change(hw, TRUE);
3154 if (ret_val) {
3156 return ret_val;
3170 int32_t ret_val;
3193 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
3194 if (ret_val)
3195 return ret_val;
3196 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9),
3198 if (ret_val)
3199 return ret_val;
3201 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9),
3203 if (ret_val)
3204 return ret_val;
3210 ret_val = em_copper_link_preconfig(hw);
3211 if (ret_val)
3212 return ret_val;
3220 ret_val = em_write_kmrn_reg(hw,
3222 if (ret_val)
3223 return ret_val;
3232 ret_val = em_copper_link_igp_setup(hw);
3233 if (ret_val)
3234 return ret_val;
3239 ret_val = em_copper_link_mgp_setup(hw);
3240 if (ret_val)
3241 return ret_val;
3243 ret_val = em_copper_link_ggp_setup(hw);
3244 if (ret_val)
3245 return ret_val;
3249 ret_val = em_copper_link_82577_setup(hw);
3250 if (ret_val)
3251 return ret_val;
3253 ret_val = em_copper_link_82580_setup(hw);
3254 if (ret_val)
3255 return ret_val;
3257 ret_val = em_copper_link_rtl8211_setup(hw);
3258 if (ret_val)
3259 return ret_val;
3266 ret_val = em_copper_link_autoneg(hw);
3267 if (ret_val)
3268 return ret_val;
3275 ret_val = em_phy_force_speed_duplex(hw);
3276 if (ret_val) {
3278 return ret_val;
3286 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3287 if (ret_val)
3288 return ret_val;
3289 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3290 if (ret_val)
3291 return ret_val;
3297 ret_val = em_copper_link_postconfig(hw);
3298 if (ret_val)
3299 return ret_val;
3319 int32_t ret_val = E1000_SUCCESS;
3325 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
3327 if (ret_val)
3328 return ret_val;
3336 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3338 if (ret_val)
3339 return ret_val;
3346 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3348 return ret_val;
3354 int32_t ret_val = E1000_SUCCESS;
3360 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
3362 if (ret_val)
3363 return ret_val;
3371 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
3373 if (ret_val)
3374 return ret_val;
3377 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3379 return ret_val;
3390 int32_t ret_val;
3396 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3397 if (ret_val)
3398 return ret_val;
3402 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL,
3404 if (ret_val)
3405 return ret_val;
3516 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3517 if (ret_val)
3518 return ret_val;
3523 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL,
3525 if (ret_val)
3526 return ret_val;
3539 int32_t ret_val;
3562 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
3563 if (ret_val)
3564 return ret_val;
3616 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3618 if (ret_val)
3619 return ret_val;
3625 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3627 if (ret_val)
3628 return ret_val;
3637 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
3638 if(ret_val) {
3641 return ret_val;
3650 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
3651 if(ret_val) {
3653 return ret_val;
3660 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
3661 if (ret_val)
3662 return ret_val;
3667 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
3668 if (ret_val)
3669 return ret_val;
3675 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
3677 if (ret_val)
3678 return ret_val;
3683 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
3685 if (ret_val)
3686 return ret_val;
3690 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
3691 if (ret_val)
3692 return ret_val;
3716 ret_val = em_read_phy_reg(hw, PHY_STATUS,
3718 if (ret_val)
3719 return ret_val;
3721 ret_val = em_read_phy_reg(hw, PHY_STATUS,
3723 if (ret_val)
3724 return ret_val;
3738 ret_val = em_phy_reset_dsp(hw);
3739 if (ret_val) {
3741 return ret_val;
3756 ret_val = em_read_phy_reg(hw, PHY_STATUS,
3758 if (ret_val)
3759 return ret_val;
3761 ret_val = em_read_phy_reg(hw, PHY_STATUS,
3763 if (ret_val)
3764 return ret_val;
3776 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
3778 if (ret_val)
3779 return ret_val;
3782 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
3784 if (ret_val)
3785 return ret_val;
3791 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3793 if (ret_val)
3794 return ret_val;
3801 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
3803 if (ret_val)
3804 return ret_val;
3809 ret_val = em_polarity_reversal_workaround(hw);
3810 if (ret_val)
3811 return ret_val;
3820 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
3821 if(ret_val) {
3823 return ret_val;
3827 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
3828 if(ret_val) {
3830 return ret_val;
3839 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
3841 if (ret_val)
3842 return ret_val;
3854 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
3856 if (ret_val)
3857 return ret_val;
3903 int32_t ret_val;
3924 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3925 if (ret_val)
3926 return ret_val;
4025 int32_t ret_val;
4042 ret_val = em_force_mac_fc(hw);
4043 if (ret_val) {
4045 return ret_val;
4062 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
4063 if (ret_val)
4064 return ret_val;
4065 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
4066 if (ret_val)
4067 return ret_val;
4077 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV,
4079 if (ret_val)
4080 return ret_val;
4081 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
4083 if (ret_val)
4084 return ret_val;
4215 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
4216 if (ret_val) {
4219 return ret_val;
4228 ret_val = em_force_mac_fc(hw);
4229 if (ret_val) {
4232 return ret_val;
4257 int32_t ret_val;
4264 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed,
4268 return (ret_val);
4306 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4307 if (ret_val)
4308 return ret_val;
4309 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4310 if (ret_val)
4311 return ret_val;
4316 ret_val = em_k1_gig_workaround_hv(hw,
4318 if (ret_val)
4319 return ret_val;
4326 ret_val = em_link_stall_workaround_hv(hw);
4327 if (ret_val)
4328 return ret_val;
4332 ret_val = em_k1_workaround_lv(hw);
4333 if (ret_val)
4334 return ret_val;
4341 ret_val = em_k1_workaround_lpt_lp(hw,
4343 if (ret_val)
4344 return ret_val;
4360 ret_val = em_set_eee_pchlan(hw);
4361 if (ret_val)
4362 return ret_val;
4380 ret_val = em_polarity_reversal_workaround(hw);
4412 ret_val = em_config_mac_to_phy(hw);
4413 if (ret_val) {
4416 return ret_val;
4425 ret_val = em_config_fc_after_link_up(hw);
4426 if (ret_val) {
4428 return ret_val;
4441 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
4442 if (ret_val) {
4445 return ret_val;
4508 ret_val = em_config_fc_after_link_up(hw);
4509 if (ret_val) {
4511 return ret_val;
4613 int32_t ret_val;
4652 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4653 if (ret_val)
4654 return ret_val;
4659 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY,
4661 if (ret_val)
4662 return ret_val;
4673 ret_val = em_configure_kmrn_for_1000(hw);
4675 ret_val = em_configure_kmrn_for_10_100(hw, *duplex);
4676 if (ret_val)
4677 return ret_val;
4682 ret_val = em_kumeran_lock_loss_workaround(hw);
4683 if (ret_val)
4684 return ret_val;
4697 int32_t ret_val;
4709 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4710 if (ret_val)
4711 return ret_val;
4712 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4713 if (ret_val)
4714 return ret_val;
4953 int32_t ret_val;
4964 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg);
4965 if (ret_val)
4970 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg);
4971 if (ret_val)
4975 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG,
4977 if (ret_val)
4981 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
4985 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg);
4986 if (ret_val)
4991 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE,
4995 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE,
4998 if (ret_val)
5009 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg);
5010 if (ret_val)
5014 return ret_val;
5024 int32_t ret_val;
5037 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F);
5038 if (ret_val) {
5045 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data);
5047 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data);
5049 if (ret_val) {
5055 return ret_val;
5068 uint32_t ret_val;
5081 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr,
5106 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
5108 if (ret_val)
5109 return ret_val;
5113 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
5115 if (ret_val)
5116 return ret_val;
5119 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg,
5122 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg,
5126 return ret_val;
5138 uint32_t ret_val;
5165 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
5167 if (ret_val) {
5169 return ret_val;
5177 ret_val = em_write_phy_reg_ex(hw,
5186 ret_val = em_write_phy_reg_ex(hw,
5192 if (ret_val) {
5194 return ret_val;
5199 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT,
5202 if (ret_val)
5203 return ret_val;
5206 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
5210 return ret_val;
5318 uint32_t ret_val;
5337 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
5339 if (ret_val) {
5341 return ret_val;
5349 ret_val = em_write_phy_reg_ex(hw,
5358 ret_val = em_write_phy_reg_ex(hw,
5364 if (ret_val) {
5366 return ret_val;
5371 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT,
5374 if (ret_val)
5375 return ret_val;
5378 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
5382 return ret_val;
5714 int32_t ret_val;
5720 ret_val = em_check_phy_reset_block(hw);
5721 if (ret_val)
5784 ret_val = em_get_phy_cfg_done(hw);
5785 if (ret_val != E1000_SUCCESS)
5786 return ret_val;
5790 ret_val = em_init_lcd_from_nvm(hw);
5792 return ret_val;
5804 int32_t ret_val = E1000_SUCCESS;
5810 return ret_val;
5812 ret_val = em_swfw_sync_acquire(hw, swfw);
5813 if (ret_val)
5814 return ret_val;
5828 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg);
5829 if (ret_val)
5854 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg);
5859 return ret_val;
5873 int32_t ret_val;
5880 ret_val = em_check_phy_reset_block(hw);
5881 if (ret_val)
5889 ret_val = em_phy_hw_reset(hw);
5890 if (ret_val)
5891 return ret_val;
5894 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
5895 if (ret_val)
5896 return ret_val;
5899 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
5900 if (ret_val)
5901 return ret_val;
5914 ret_val = em_hv_phy_workarounds_ich8lan(hw);
5915 if (ret_val)
5916 return ret_val;
5918 ret_val = em_lv_phy_workarounds_ich8lan(hw);
5919 if (ret_val)
5920 return ret_val;
5924 ret_val = em_oem_bits_config_pchlan(hw, TRUE);
5925 if (ret_val)
5926 return ret_val;
5937 ret_val = em_initialize_M88E1512_phy(hw);
5938 if (ret_val)
5939 return ret_val;
5962 int32_t ret_val;
5972 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
5973 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
5978 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG,
5980 if (ret_val)
5981 return ret_val;
5983 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
5984 if (ret_val)
5985 return ret_val;
6014 int32_t phy_init_status, ret_val;
6019 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high);
6020 if (ret_val)
6021 return ret_val;
6025 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low);
6026 if (ret_val)
6027 return ret_val;
6158 int32_t ret_val, i;
6209 ret_val = em_phy_hw_reset(hw);
6210 if (ret_val)
6211 return ret_val;
6241 ret_val = em_match_gig_phy(hw);
6242 if (ret_val == E1000_SUCCESS)
6256 int32_t ret_val;
6261 ret_val = em_write_phy_reg(hw, 29, 0x001d);
6262 if (ret_val)
6265 ret_val = em_write_phy_reg(hw, 30, 0x00c1);
6266 if (ret_val)
6268 ret_val = em_write_phy_reg(hw, 30, 0x0000);
6269 if (ret_val)
6271 ret_val = E1000_SUCCESS;
6274 return ret_val;
6289 int32_t ret_val = E1000_SUCCESS;
6503 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1,
6505 if (ret_val)
6506 return ret_val;
6532 return ret_val;
7749 int32_t ret_val, dft_ret_val;
7755 ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14));
7756 if (ret_val)
7757 return ret_val;
7768 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, &data);
7769 if (ret_val)
7771 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL,
7773 if (ret_val)
7776 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, &data);
7777 if (ret_val)
7782 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, data);
7783 if (ret_val)
7789 ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL, data);
7790 if (ret_val)
7795 ret_val = em_write_phy_reg(hw, I2_MODE_CTRL, data);
7796 if (ret_val)
7806 ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data);
7807 if (ret_val)
7810 ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00);
7811 if (ret_val)
7815 ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL, data & ~(1 << 10));
7816 if (ret_val)
7822 if (ret_val)
7823 return ret_val;
8388 int32_t ret_val;
8415 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS,
8417 if (ret_val)
8506 int32_t ret_val;
8519 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
8521 if (ret_val)
8522 return ret_val;
8557 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
8559 if (ret_val)
8560 return ret_val;
8594 ret_val = em_read_phy_reg(hw, agc_reg_array[i],
8596 if (ret_val)
8597 return ret_val;
8645 ret_val = em_read_phy_reg(hw, agc_reg_array[i],
8647 if (ret_val)
8648 return ret_val;
8708 int32_t ret_val;
8715 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
8717 if (ret_val)
8718 return ret_val;
8726 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
8728 if (ret_val)
8729 return ret_val;
8754 int32_t ret_val;
8766 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
8767 if (ret_val) {
8769 return ret_val;
8773 ret_val = em_get_cable_length(hw, &min_length, &max_length);
8774 if (ret_val)
8775 return ret_val;
8782 ret_val = em_read_phy_reg(hw,
8784 if (ret_val)
8785 return ret_val;
8790 ret_val = em_write_phy_reg(hw,
8792 if (ret_val)
8793 return ret_val;
8804 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS,
8806 if (ret_val)
8807 return ret_val;
8811 ret_val = em_read_phy_reg(hw,
8813 if (ret_val)
8814 return ret_val;
8823 ret_val = em_write_phy_reg(hw,
8826 if (ret_val)
8827 return ret_val;
8842 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
8844 if (ret_val)
8845 return ret_val;
8848 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
8850 if (ret_val)
8851 return ret_val;
8855 ret_val = em_write_phy_reg(hw, 0x0000,
8857 if (ret_val)
8858 return ret_val;
8860 ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
8862 if (ret_val)
8863 return ret_val;
8869 ret_val = em_write_phy_reg(hw,
8871 if (ret_val)
8872 return ret_val;
8875 ret_val = em_write_phy_reg(hw, 0x0000,
8877 if (ret_val)
8878 return ret_val;
8883 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
8885 if (ret_val)
8886 return ret_val;
8895 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
8897 if (ret_val)
8898 return ret_val;
8901 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
8903 if (ret_val)
8904 return ret_val;
8908 ret_val = em_write_phy_reg(hw, 0x0000,
8910 if (ret_val)
8911 return ret_val;
8912 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
8914 if (ret_val)
8915 return ret_val;
8917 ret_val = em_write_phy_reg(hw, 0x0000,
8919 if (ret_val)
8920 return ret_val;
8925 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
8927 if (ret_val)
8928 return ret_val;
8947 int32_t ret_val;
8953 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
8955 if (ret_val) {
8956 return ret_val;
8960 ret_val = em_write_phy_reg(hw,
8962 if (ret_val)
8963 return ret_val;
8964 ret_val = em_write_phy_reg(hw,
8966 if (ret_val)
8967 return ret_val;
8992 int32_t ret_val;
9005 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
9006 if (ret_val)
9007 return ret_val;
9016 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
9018 if (ret_val)
9019 return ret_val;
9026 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
9028 if (ret_val)
9029 return ret_val;
9036 ret_val = em_write_phy_reg(hw,
9038 if (ret_val)
9039 return ret_val;
9049 ret_val = em_read_phy_reg(hw,
9051 if (ret_val)
9052 return ret_val;
9055 ret_val = em_write_phy_reg(hw,
9057 if (ret_val)
9058 return ret_val;
9060 ret_val = em_read_phy_reg(hw,
9062 if (ret_val)
9063 return ret_val;
9066 ret_val = em_write_phy_reg(hw,
9068 if (ret_val)
9069 return ret_val;
9078 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
9080 if (ret_val)
9081 return ret_val;
9088 ret_val = em_write_phy_reg(hw,
9090 if (ret_val)
9091 return ret_val;
9096 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
9098 if (ret_val)
9099 return ret_val;
9102 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
9104 if (ret_val)
9105 return ret_val;
9128 int32_t ret_val;
9138 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
9140 if (ret_val)
9141 return ret_val;
9150 ret_val = em_write_phy_reg(hw,
9152 if (ret_val)
9153 return ret_val;
9162 ret_val = em_read_phy_reg(hw,
9164 if (ret_val)
9165 return ret_val;
9168 ret_val = em_write_phy_reg(hw,
9170 if (ret_val)
9171 return ret_val;
9173 ret_val = em_read_phy_reg(hw,
9175 if (ret_val)
9176 return ret_val;
9179 ret_val = em_write_phy_reg(hw,
9181 if (ret_val)
9182 return ret_val;
9190 ret_val = em_write_phy_reg(hw,
9192 if (ret_val)
9193 return ret_val;
9197 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
9199 if (ret_val)
9200 return ret_val;
9203 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
9205 if (ret_val)
9206 return ret_val;
9224 int32_t ret_val = E1000_SUCCESS;
9229 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg);
9230 if (ret_val)
9239 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg);
9242 return ret_val;
9253 int32_t ret_val;
9268 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
9269 if (ret_val)
9270 return ret_val;
9272 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
9273 if (ret_val)
9274 return ret_val;
9276 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
9277 if (ret_val)
9278 return ret_val;
9281 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
9282 if (ret_val)
9283 return ret_val;
9287 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
9288 if (ret_val)
9289 return ret_val;
9291 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
9292 if (ret_val)
9293 return ret_val;
9296 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
9297 if (ret_val)
9298 return ret_val;
9300 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
9301 if (ret_val)
9302 return ret_val;
9413 int32_t ret_val, checksum;
9418 ret_val = em_mng_enable_host_if(hw);
9419 if (ret_val == E1000_SUCCESS) {
9420 ret_val = em_host_if_read_cookie(hw, buffer);
9421 if (ret_val == E1000_SUCCESS) {
9444 int32_t ret_val;
9450 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
9451 if (ret_val)
9452 return ret_val;
9453 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
9454 if (ret_val)
9455 return ret_val;
9457 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
9458 if (ret_val)
9459 return ret_val;
9468 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9469 if (ret_val)
9470 return ret_val;
9472 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9473 if (ret_val)
9474 return ret_val;
9486 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
9487 if (ret_val)
9488 return ret_val;
9490 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
9491 if (ret_val)
9492 return ret_val;
9494 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
9495 if (ret_val)
9496 return ret_val;
9498 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
9499 if (ret_val)
9500 return ret_val;
9502 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
9503 if (ret_val)
9504 return ret_val;
9513 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9514 if (ret_val)
9515 return ret_val;
9517 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
9518 if (ret_val)
9519 return ret_val;
10024 int32_t ret_val;
10040 ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword);
10041 if (ret_val)
10042 return ret_val;
10051 ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset,
10053 if (ret_val)
10054 return ret_val;
10083 ret_val = em_read_ich8_byte(hw, act_offset,
10085 if (ret_val)
10086 return ret_val;
10094 ret_val = em_read_ich8_byte(hw, act_offset +
10097 if (ret_val)
10098 return ret_val;
10979 int32_t ret_val = E1000_SUCCESS;
10987 ret_val = em_read_invm_word_i210(hw, offset, data);
10988 if (ret_val != E1000_SUCCESS) {
10991 ret_val = E1000_SUCCESS;
10995 ret_val = em_read_invm_word_i210(hw, offset, data);
10996 if (ret_val != E1000_SUCCESS) {
10998 ret_val = E1000_SUCCESS;
11002 ret_val = em_read_invm_word_i210(hw, offset, data);
11003 if (ret_val != E1000_SUCCESS) {
11005 ret_val = E1000_SUCCESS;
11009 ret_val = em_read_invm_word_i210(hw, offset, data);
11010 if (ret_val != E1000_SUCCESS) {
11012 ret_val = E1000_SUCCESS;
11016 ret_val = em_read_invm_word_i210(hw, offset, data);
11017 if (ret_val != E1000_SUCCESS) {
11019 ret_val = E1000_SUCCESS;
11023 ret_val = em_read_invm_word_i210(hw, offset, data);
11024 if (ret_val != E1000_SUCCESS) {
11026 ret_val = E1000_SUCCESS;
11035 return ret_val;
11081 uint32_t ret_val = E1000_SUCCESS;
11089 ret_val =
11091 if (ret_val)
11092 return ret_val;
11094 ret_val =
11096 if (ret_val)
11097 return ret_val;
11099 ret_val = em_get_software_flag(hw);
11100 if (ret_val != E1000_SUCCESS)
11101 return ret_val;
11103 ret_val =
11109 return ret_val;
11123 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask;
11174 ret_val = em_init_lcd_from_nvm_config_region(hw,
11176 if (ret_val)
11177 return ret_val;
11198 int32_t ret_val = E1000_SUCCESS;
11226 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
11229 if (ret_val)
11234 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
11246 return ret_val;
11255 int32_t ret_val;
11259 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data);
11260 if (ret_val)
11261 return ret_val;
11265 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data);
11267 return ret_val;
11276 int32_t ret_val = E1000_SUCCESS;
11289 ret_val = em_set_mdio_slow_mode_hv(hw);
11290 if (ret_val)
11324 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431);
11325 if (ret_val)
11329 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204);
11330 if (ret_val)
11341 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140);
11352 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400);
11353 if (ret_val)
11355 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400);
11356 if (ret_val)
11361 ret_val = em_swfw_sync_acquire(hw, swfw);
11362 if (ret_val)
11366 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
11368 if (ret_val)
11372 ret_val = em_read_phy_reg(hw,
11375 if (ret_val)
11377 ret_val = em_write_phy_reg(hw,
11382 return ret_val;
11399 int32_t ret_val = E1000_SUCCESS;
11411 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data);
11412 if (ret_val)
11427 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL,
11429 if (ret_val)
11432 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL,
11436 return ret_val;
11450 int32_t ret_val;
11459 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data);
11460 if (ret_val)
11461 return ret_val;
11468 ret_val = em_read_phy_reg(hw, BM_CS_STATUS,
11470 if (ret_val)
11471 return ret_val;
11484 ret_val = em_read_phy_reg(hw, HV_M_STATUS,
11486 if (ret_val)
11487 return ret_val;
11500 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19),
11502 if (ret_val)
11503 return ret_val;
11507 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19),
11509 if (ret_val)
11510 return ret_val;
11513 ret_val = em_configure_k1_ich8lan(hw, k1_enable);
11515 return ret_val;
11522 int32_t ret_val;
11526 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data);
11527 if (ret_val)
11528 return ret_val;
11560 int32_t ret_val = E1000_SUCCESS;
11564 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11566 if (ret_val)
11567 return ret_val;
11569 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11571 if (ret_val)
11572 return ret_val;
11579 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11589 ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®);
11590 if (ret_val)
11591 return ret_val;
11611 ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg);
11612 if (ret_val)
11613 return ret_val;
11619 return ret_val;
11663 int32_t ret_val = E1000_SUCCESS;
11669 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11671 if (ret_val)
11679 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
11681 if (ret_val)
11699 return ret_val;
11709 int32_t ret_val = E1000_SUCCESS;
11718 ret_val = em_set_mdio_slow_mode_hv(hw);
11721 ret_val = em_swfw_sync_acquire(hw, swfw);
11722 if (ret_val)
11724 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR,
11726 if (ret_val)
11729 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA,
11731 if (ret_val)
11733 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR,
11735 if (ret_val)
11738 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA,
11744 return ret_val;
11750 int32_t ret_val = E1000_SUCCESS;
11773 return ret_val;
11786 int32_t ret_val = E1000_SUCCESS;
11795 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg);
11796 if (ret_val)
11804 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg);
11806 return ret_val;
11818 int32_t ret_val = E1000_SUCCESS;
11827 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF);
11828 if (ret_val)
11831 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B);
11832 if (ret_val)
11835 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144);
11836 if (ret_val)
11839 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28);
11840 if (ret_val)
11843 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146);
11844 if (ret_val)
11847 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233);
11848 if (ret_val)
11851 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D);
11852 if (ret_val)
11855 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C);
11856 if (ret_val)
11859 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159);
11860 if (ret_val)
11864 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB);
11865 if (ret_val)
11868 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D);
11869 if (ret_val)
11873 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12);
11874 if (ret_val)
11878 ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001);
11879 if (ret_val)
11883 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0);
11884 if (ret_val)
11887 ret_val = em_phy_hw_reset(hw);
11888 if (ret_val) {
11890 return ret_val;
11895 return ret_val;