Lines Matching defs:phy_reg
1427 uint16_t phy_reg;
1480 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg);
1491 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL, &phy_reg);
1495 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1496 em_write_phy_reg(hw, CV_SMB_CTRL, phy_reg);
1506 ret_val = em_read_phy_reg(hw, HV_PM_CTRL, &phy_reg);
1509 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1510 em_write_phy_reg(hw, HV_PM_CTRL, phy_reg);
1513 ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1, &phy_reg);
1516 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1524 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg);
1527 phy_reg |= I218_ULP_CONFIG1_START;
1528 em_write_phy_reg(hw, I218_ULP_CONFIG1, phy_reg);
4955 uint16_t phy_reg = 0;
4964 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg);
4969 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
4970 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg);
4976 phy_reg | BM_WUC_ENABLE_BIT);
5009 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg);
7751 uint16_t data, phy_reg;
7754 em_read_phy_reg(hw, I2_DFT_CTRL, &phy_reg);
7755 ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14));
7821 dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg & ~(1 << 14));
11787 uint16_t phy_reg;
11795 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg);
11800 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
11802 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
11804 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg);