Lines Matching defs:phy_data
2331 uint16_t phy_data;
2362 &phy_data);
2363 phy_data |= 0x00000008;
2365 phy_data);
2399 uint16_t phy_data;
2446 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2453 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
2459 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2463 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2466 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2470 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2474 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2494 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2498 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2500 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2505 &phy_data);
2509 phy_data &= ~CR_1000T_MS_ENABLE;
2511 phy_data);
2515 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2520 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2521 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master :
2526 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2529 phy_data |= CR_1000T_MS_ENABLE;
2530 phy_data &= ~(CR_1000T_MS_VALUE);
2533 phy_data &= ~CR_1000T_MS_ENABLE;
2538 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2554 uint16_t phy_data;
2562 &phy_data);
2566 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2568 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2571 phy_data);
2580 &phy_data);
2585 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2589 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2592 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2596 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2604 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2606 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2608 phy_data);
2630 &phy_data);
2634 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2636 phy_data);
2646 &phy_data);
2656 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2658 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2663 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2667 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2669 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2679 &phy_data);
2682 phy_data |= GG82563_ICR_DIS_PADDING;
2684 phy_data);
2700 uint16_t phy_data;
2717 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2722 phy_data |= 0x00000008;
2724 phy_data);
2729 &phy_data);
2733 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX;
2738 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2744 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2748 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2751 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2754 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2758 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2765 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
2767 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
2771 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
2773 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2786 &phy_data);
2791 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL;
2792 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL;
2794 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2799 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2800 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2802 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2807 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
2809 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
2812 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2834 &phy_data);
2839 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
2840 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
2842 phy_data);
2864 uint16_t phy_data;
2872 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data);
2876 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX |
2879 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data);
2903 uint16_t phy_data;
2913 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data);
2917 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX |
2920 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data);
2930 uint16_t phy_data;
2941 phy_data = 0;
2943 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
2949 hw->phy_addr, phy_data);
2950 phy_data |= RGEPHY_CR_ASSERT_CRS;
2952 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
2958 phy_data = 0; /* LED Control Register 0x18 */
2959 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data);
2965 phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */
2966 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data);
2972 phy_data = 0;
2973 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data);
2979 phy_data |= 0x0010; /* LED active Low */
2980 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data);
2986 phy_data = 0;
2987 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data);
2994 phy_data = RGEPHY_PS_PAGE_2;
2995 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data);
3001 phy_data = 0x0000;
3002 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data);
3011 phy_data = 0;
3012 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data);
3018 phy_data &= 0xF000;
3019 phy_data |= 0x0F24;
3020 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data);
3025 phy_data = 0;
3026 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data);
3031 DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data);
3035 phy_data = 0;
3036 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data);
3043 phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK |
3046 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data);
3064 uint16_t phy_data;
3093 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
3097 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
3098 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
3172 uint16_t phy_data;
3286 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3289 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
3293 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0;
3295 if (phy_data & MII_SR_LINK_STATUS) {
3542 uint16_t phy_data;
3617 &phy_data);
3624 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
3626 phy_data);
3630 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
3637 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
3649 phy_data |= RGEPHY_CR_MDI_MASK; // enable MDIX
3650 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
3660 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
3664 phy_data &= ~IFE_PMC_AUTO_MDIX;
3665 phy_data &= ~IFE_PMC_FORCE_MDIX;
3667 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
3676 &phy_data);
3680 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
3681 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
3684 phy_data);
3777 &phy_data);
3781 phy_data |= M88E1000_EPSCR_TX_CLK_25;
3783 phy_data);
3792 &phy_data);
3797 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX;
3799 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
3802 phy_data);
3820 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data);
3826 phy_data &= ~RGEPHY_CR_ASSERT_CRS;
3827 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data);
3840 &phy_data);
3844 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
3847 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
3849 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
3852 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
3855 phy_data);
3904 uint16_t phy_data;
3924 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3928 if (phy_data & M88E1000_PSSR_DPLX)
3938 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3940 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
4258 uint16_t phy_data;
4306 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4309 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4313 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0;
4322 if (phy_data & MII_SR_LINK_STATUS) {
4614 uint16_t phy_data;
4652 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4656 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
4660 &phy_data);
4664 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
4666 !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
4699 uint16_t phy_data;
4709 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4712 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
4715 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
4951 uint16_t *phy_data, boolean_t read)
4992 phy_data);
4996 *phy_data);
5022 uint16_t *phy_data, boolean_t read)
5045 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data);
5047 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data);
5065 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data,
5082 phy_data, read);
5103 (*phy_data & (1 << 11))) {
5120 phy_data);
5123 *phy_data);
5136 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)
5149 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE));
5207 phy_data);
5214 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)
5226 return em_read_phy_reg_i2c(hw, reg_addr, phy_data);
5233 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num,
5268 *phy_data = (uint16_t) mdic;
5303 *phy_data = em_shift_in_mdi_bits(hw);
5316 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)
5328 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE));
5379 phy_data);
5386 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)
5398 return em_write_phy_reg_i2c(hw, reg_addr, phy_data);
5406 reg_addr, phy_data);
5416 mdic = (((uint32_t) phy_data) |
5459 mdic |= (uint32_t) phy_data;
5874 uint16_t phy_data;
5894 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
5898 phy_data |= MII_CR_RESET;
5899 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
5965 uint16_t phy_data;
5972 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
5973 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
5975 if (phy_data & MII_SR_LINK_STATUS) {
5979 &phy_data);
5983 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
5988 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
8344 uint16_t phy_data;
8346 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data);
8347 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data);
8348 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data);
8349 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data);
8350 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data);
8351 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data);
8352 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data);
8353 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data);
8354 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data);
8355 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data);
8356 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data);
8357 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data);
8358 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data);
8359 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data);
8508 uint16_t i, phy_data;
8520 &phy_data);
8523 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
8558 &phy_data);
8561 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
8595 &phy_data);
8599 cur_agc_value = phy_data >>
8646 &phy_data);
8655 cur_agc_index = (phy_data >>
8709 uint16_t phy_data;
8716 &phy_data);
8720 hw->speed_downgraded = (phy_data &
8727 &phy_data);
8731 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
8755 uint16_t phy_data, phy_saved_data, speed, duplex, i;
8783 dsp_reg_array[i], &phy_data);
8787 phy_data &=
8791 dsp_reg_array[i], phy_data);
8805 &phy_data);
8812 PHY_1000T_STATUS, &phy_data);
8816 idle_errs += (phy_data &
8861 &phy_data);
8865 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
8866 phy_data |=
8870 dsp_reg_array[i], phy_data);
8993 uint16_t phy_data;
9005 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
9017 &phy_data);
9025 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
9027 phy_data);
9035 phy_data &= ~IGP02E1000_PM_D3_LPLU;
9037 IGP02E1000_PHY_POWER_MGMT, phy_data);
9050 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
9054 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
9056 IGP01E1000_PHY_PORT_CONFIG, phy_data);
9061 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
9065 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
9067 IGP01E1000_PHY_PORT_CONFIG, phy_data);
9077 phy_data |= IGP01E1000_GMII_FLEX_SPD;
9079 phy_data);
9087 phy_data |= IGP02E1000_PM_D3_LPLU;
9089 IGP02E1000_PHY_POWER_MGMT, phy_data);
9097 &phy_data);
9101 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
9103 phy_data);
9129 uint16_t phy_data;
9139 &phy_data);
9149 phy_data &= ~IGP02E1000_PM_D0_LPLU;
9151 IGP02E1000_PHY_POWER_MGMT, phy_data);
9163 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
9167 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
9169 IGP01E1000_PHY_PORT_CONFIG, phy_data);
9174 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
9178 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
9180 IGP01E1000_PHY_PORT_CONFIG, phy_data);
9189 phy_data |= IGP02E1000_PM_D0_LPLU;
9191 IGP02E1000_PHY_POWER_MGMT, phy_data);
9198 &phy_data);
9202 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
9204 phy_data);
9255 uint16_t phy_data;
9276 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
9280 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
9281 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
9291 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
9295 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
9296 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
11277 uint16_t phy_data;
11374 &phy_data);
11379 phy_data & 0x00FF);
11400 uint16_t phy_data;
11406 em_read_phy_reg(hw, PHY_CTRL, &phy_data);
11407 if (phy_data & E1000_PHY_CTRL_LOOPBACK)
11411 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data);
11415 phy_data &= BM_CS_STATUS_LINK_UP |
11419 if (phy_data != (BM_CS_STATUS_LINK_UP |
11451 uint16_t phy_data;
11459 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data);
11463 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE;
11469 &phy_data);
11473 phy_data &= BM_CS_STATUS_LINK_UP |
11477 if (phy_data == (BM_CS_STATUS_LINK_UP |
11485 &phy_data);
11489 phy_data &= HV_M_STATUS_LINK_UP |
11493 if (phy_data == (HV_M_STATUS_LINK_UP |
11523 uint16_t phy_data;
11526 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data);
11530 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
11535 if (phy_data & HV_M_STATUS_SPEED_1000)