Lines Matching defs:ctrl

928 	uint32_t ctrl;
986 	ctrl = E1000_READ_REG(hw, CTRL);
990 		E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
1044 		E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
1049 		E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
1068 			ctrl |= E1000_CTRL_PHY_RST;
1079 		E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1092 		E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1564 	uint32_t ctrl;
1600 			ctrl = E1000_READ_REG(hw, CTRL);
1601 			ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
1602 			ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
1603 			E1000_WRITE_REG(hw, CTRL, ctrl);
1605 			ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
1606 			E1000_WRITE_REG(hw, CTRL, ctrl);
1702 		ctrl = E1000_READ_REG(hw, CTRL);
1703 		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1761 			ctrl = E1000_READ_REG(hw, TXDCTL(que->me));
1762 			ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) |
1764 			E1000_WRITE_REG(hw, TXDCTL(que->me), ctrl);
1817 			ctrl = E1000_READ_REG(hw, TXDCTL(1));
1818 			ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 
1820 			E1000_WRITE_REG(hw, TXDCTL(1), ctrl);
2128 	uint32_t ctrl, ctrl_ext, reg;
2161 	ctrl = E1000_READ_REG(hw, CTRL);
2170 	ctrl &= ~(E1000_CTRL_LRST);
2174 		ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
2273 	E1000_WRITE_REG(hw, CTRL, ctrl);
2329 	uint32_t ctrl;
2334 	ctrl = E1000_READ_REG(hw, CTRL);
2342 		ctrl |= E1000_CTRL_SLU;
2343 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2344 		E1000_WRITE_REG(hw, CTRL, ctrl);
2346 		ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 
2348 		E1000_WRITE_REG(hw, CTRL, ctrl);
3538 	uint32_t ctrl;
3552 	ctrl = E1000_READ_REG(hw, CTRL);
3555 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3556 	ctrl &= ~(DEVICE_SPEED_MASK);
3559 	ctrl &= ~E1000_CTRL_ASDE;
3577 		ctrl |= E1000_CTRL_FD;
3585 		ctrl &= ~E1000_CTRL_FD;
3594 		ctrl |= E1000_CTRL_SPD_100;
3600 		ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
3609 	E1000_WRITE_REG(hw, CTRL, ctrl);
3902 	uint32_t ctrl;
3917 	ctrl = E1000_READ_REG(hw, CTRL);
3918 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3919 	ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3929 		ctrl |= E1000_CTRL_FD;
3931 		ctrl &= ~E1000_CTRL_FD;
3939 		ctrl |= E1000_CTRL_SPD_1000;
3941 		ctrl |= E1000_CTRL_SPD_100;
3944 	E1000_WRITE_REG(hw, CTRL, ctrl);
3962 	uint32_t ctrl;
3966 	ctrl = E1000_READ_REG(hw, CTRL);
3986 		ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3989 		ctrl &= (~E1000_CTRL_TFCE);
3990 		ctrl |= E1000_CTRL_RFCE;
3993 		ctrl &= (~E1000_CTRL_RFCE);
3994 		ctrl |= E1000_CTRL_TFCE;
3997 		ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
4006 		ctrl &= (~E1000_CTRL_TFCE);
4008 	E1000_WRITE_REG(hw, CTRL, ctrl);
4252 	uint32_t ctrl;
4271 	ctrl = E1000_READ_REG(hw, CTRL);
4490 	    ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
4503 		ctrl = E1000_READ_REG(hw, CTRL);
4504 		ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
4505 		E1000_WRITE_REG(hw, CTRL, ctrl);
4522 	    (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
4525 		E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
4727  * ctrl - Device control register's current value
4730 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl)
4736 	E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
4745  * ctrl - Device control register's current value
4748 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl)
4754 	E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
4771 	uint32_t ctrl;
4782 	ctrl = E1000_READ_REG(hw, CTRL);
4787 	ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4797 			ctrl |= E1000_CTRL_MDIO;
4799 			ctrl &= ~E1000_CTRL_MDIO;
4801 		E1000_WRITE_REG(hw, CTRL, ctrl);
4806 		em_raise_mdi_clk(hw, &ctrl);
4807 		em_lower_mdi_clk(hw, &ctrl);
4823 	uint32_t ctrl;
4835 	ctrl = E1000_READ_REG(hw, CTRL);
4840 	ctrl &= ~E1000_CTRL_MDIO_DIR;
4841 	ctrl &= ~E1000_CTRL_MDIO;
4843 	E1000_WRITE_REG(hw, CTRL, ctrl);
4850 	em_raise_mdi_clk(hw, &ctrl);
4851 	em_lower_mdi_clk(hw, &ctrl);
4855 		em_raise_mdi_clk(hw, &ctrl);
4856 		ctrl = E1000_READ_REG(hw, CTRL);
4858 		if (ctrl & E1000_CTRL_MDIO)
4860 		em_lower_mdi_clk(hw, &ctrl);
4863 	em_raise_mdi_clk(hw, &ctrl);
4864 	em_lower_mdi_clk(hw, &ctrl);
5712 	uint32_t ctrl, ctrl_ext;
5739 		ctrl = E1000_READ_REG(hw, CTRL);
5740 		E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
5748 		E1000_WRITE_REG(hw, CTRL, ctrl);
9540 	uint32_t ctrl;
9546 	ctrl = E1000_READ_REG(hw, CTRL);
9547 	ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
9548 	E1000_WRITE_REG(hw, CTRL, ctrl);