Lines Matching full:l

752 		#define STATUS_ATTN_BITS_LINK_STATE		(1L<<0)
753 		#define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT	(1L<<1)
754 		#define STATUS_ATTN_BITS_TX_BD_READ_ABORT	(1L<<2)
755 		#define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT	(1L<<3)
756 		#define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT	(1L<<4)
757 		#define STATUS_ATTN_BITS_TX_DMA_ABORT		(1L<<5)
758 		#define STATUS_ATTN_BITS_TX_PATCHUP_ABORT	(1L<<6)
759 		#define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT	(1L<<7)
760 		#define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT	(1L<<8)
761 		#define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT	(1L<<9)
762 		#define STATUS_ATTN_BITS_RX_MBUF_ABORT		(1L<<10)
763 		#define STATUS_ATTN_BITS_RX_LOOKUP_ABORT	(1L<<11)
764 		#define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT	(1L<<12)
765 		#define STATUS_ATTN_BITS_RX_V2P_ABORT		(1L<<13)
766 		#define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT	(1L<<14)
767 		#define STATUS_ATTN_BITS_RX_DMA_ABORT		(1L<<15)
768 		#define STATUS_ATTN_BITS_COMPLETION_ABORT	(1L<<16)
769 		#define STATUS_ATTN_BITS_HOST_COALESCE_ABORT	(1L<<17)
770 		#define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT	(1L<<18)
771 		#define STATUS_ATTN_BITS_CONTEXT_ABORT		(1L<<19)
772 		#define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT	(1L<<20)
773 		#define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT	(1L<<21)
774 		#define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT	(1L<<22)
775 		#define STATUS_ATTN_BITS_MAC_ABORT		(1L<<23)
776 		#define STATUS_ATTN_BITS_TIMER_ABORT		(1L<<24)
777 		#define STATUS_ATTN_BITS_DMAE_ABORT		(1L<<25)
778 		#define STATUS_ATTN_BITS_FLSH_ABORT		(1L<<26)
779 		#define STATUS_ATTN_BITS_GRC_ABORT		(1L<<27)
780 		#define STATUS_ATTN_BITS_PARITY_ERROR		(1L<<31)
1060 #define BNX_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP	 		(1L<<2)
1061 #define BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP	 (1L<<3)
1062 #define BNX_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA		 (1L<<5)
1063 #define BNX_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP	 (1L<<6)
1064 #define BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA		 (1L<<7)
1065 #define BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ		 (1L<<8)
1066 #define BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY		 (1L<<9)
1073 #define BNX_PCICFG_MISC_STATUS_INTA_VALUE		 (1L<<0)
1074 #define BNX_PCICFG_MISC_STATUS_32BIT_DET		 (1L<<1)
1075 #define BNX_PCICFG_MISC_STATUS_M66EN			 (1L<<2)
1076 #define BNX_PCICFG_MISC_STATUS_PCIX_DET		 (1L<<3)
1078 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_66		 (0L<<4)
1079 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_100		 (1L<<4)
1080 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_133		 (2L<<4)
1081 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE	 (3L<<4)
1085 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
1086 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
1087 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
1088 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
1089 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
1090 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
1091 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
1092 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)
1094 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE	 (1L<<6)
1095 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT	 (1L<<7)
1097 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)
1098 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12	 (1L<<8)
1099 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6	 (2L<<8)
1100 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62	 (4L<<8)
1101 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD	 (1L<<11)
1103 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)
1104 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)
1105 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)
1106 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)
1107 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)
1108 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP	 (1L<<16)
1109 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP	 (1L<<17)
1110 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18	 (1L<<18)
1111 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET	 (1L<<19)
1118 #define BNX_PCICFG_INT_ACK_CMD_INDEX_VALID		 (1L<<16)
1119 #define BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM	 (1L<<17)
1120 #define BNX_PCICFG_INT_ACK_CMD_MASK_INT		 (1L<<18)
1137 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_OFF		 (0L<<8)
1138 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_16		 (1L<<8)
1139 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_32		 (2L<<8)
1140 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_64		 (3L<<8)
1141 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_128		 (4L<<8)
1142 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_256		 (5L<<8)
1143 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_512		 (6L<<8)
1144 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_1024		 (7L<<8)
1146 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_OFF		 (0L<<11)
1147 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_16		 (1L<<11)
1148 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_32		 (2L<<11)
1149 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_64		 (3L<<11)
1150 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_128		 (4L<<11)
1151 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_256		 (5L<<11)
1152 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_512		 (6L<<11)
1153 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_1024		 (7L<<11)
1157 #define BNX_PCI_CONFIG_2_BAR1_SIZE_DISABLED		 (0L<<0)
1158 #define BNX_PCI_CONFIG_2_BAR1_SIZE_64K			 (1L<<0)
1159 #define BNX_PCI_CONFIG_2_BAR1_SIZE_128K		 (2L<<0)
1160 #define BNX_PCI_CONFIG_2_BAR1_SIZE_256K		 (3L<<0)
1161 #define BNX_PCI_CONFIG_2_BAR1_SIZE_512K		 (4L<<0)
1162 #define BNX_PCI_CONFIG_2_BAR1_SIZE_1M			 (5L<<0)
1163 #define BNX_PCI_CONFIG_2_BAR1_SIZE_2M			 (6L<<0)
1164 #define BNX_PCI_CONFIG_2_BAR1_SIZE_4M			 (7L<<0)
1165 #define BNX_PCI_CONFIG_2_BAR1_SIZE_8M			 (8L<<0)
1166 #define BNX_PCI_CONFIG_2_BAR1_SIZE_16M			 (9L<<0)
1167 #define BNX_PCI_CONFIG_2_BAR1_SIZE_32M			 (10L<<0)
1168 #define BNX_PCI_CONFIG_2_BAR1_SIZE_64M			 (11L<<0)
1169 #define BNX_PCI_CONFIG_2_BAR1_SIZE_128M		 (12L<<0)
1170 #define BNX_PCI_CONFIG_2_BAR1_SIZE_256M		 (13L<<0)
1171 #define BNX_PCI_CONFIG_2_BAR1_SIZE_512M		 (14L<<0)
1172 #define BNX_PCI_CONFIG_2_BAR1_SIZE_1G			 (15L<<0)
1173 #define BNX_PCI_CONFIG_2_BAR1_64ENA			 (1L<<4)
1174 #define BNX_PCI_CONFIG_2_EXP_ROM_RETRY			 (1L<<5)
1175 #define BNX_PCI_CONFIG_2_CFG_CYCLE_RETRY		 (1L<<6)
1176 #define BNX_PCI_CONFIG_2_FIRST_CFG_DONE		 (1L<<7)
1178 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED		 (0L<<8)
1179 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1K		 (1L<<8)
1180 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2K		 (2L<<8)
1181 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4K		 (3L<<8)
1182 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8K		 (4L<<8)
1183 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16K		 (5L<<8)
1184 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_32K		 (6L<<8)
1185 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_64K		 (7L<<8)
1186 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_128K		 (8L<<8)
1187 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_256K		 (9L<<8)
1188 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_512K		 (10L<<8)
1189 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1M		 (11L<<8)
1190 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2M		 (12L<<8)
1191 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4M		 (13L<<8)
1192 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8M		 (14L<<8)
1193 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16M		 (15L<<8)
1196 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_512		 (0L<<21)
1197 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_1K		 (1L<<21)
1198 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_2K		 (2L<<21)
1199 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_4K		 (3L<<21)
1200 #define BNX_PCI_CONFIG_2_FORCE_32_BIT_MSTR		 (1L<<23)
1201 #define BNX_PCI_CONFIG_2_FORCE_32_BIT_TGT		 (1L<<24)
1202 #define BNX_PCI_CONFIG_2_KEEP_REQ_ASSERT		 (1L<<25)
1206 #define BNX_PCI_CONFIG_3_FORCE_PME			 (1L<<24)
1207 #define BNX_PCI_CONFIG_3_PME_STATUS			 (1L<<25)
1208 #define BNX_PCI_CONFIG_3_PME_ENABLE			 (1L<<26)
1210 #define BNX_PCI_CONFIG_3_VAUX_PRESET			 (1L<<30)
1211 #define BNX_PCI_CONFIG_3_PCI_POWER			 (1L<<31)
1229 #define BNX_PCI_EXP_ROM_ADDR_REQ			 (1L<<31)
1233 #define BNX_PCI_VPD_INTF_INTF_REQ			 (1L<<0)
1254 #define BNX_PCI_ID_VAL4_CAP_ENA_0			 (0L<<0)
1255 #define BNX_PCI_ID_VAL4_CAP_ENA_1			 (1L<<0)
1256 #define BNX_PCI_ID_VAL4_CAP_ENA_2			 (2L<<0)
1257 #define BNX_PCI_ID_VAL4_CAP_ENA_3			 (3L<<0)
1258 #define BNX_PCI_ID_VAL4_CAP_ENA_4			 (4L<<0)
1259 #define BNX_PCI_ID_VAL4_CAP_ENA_5			 (5L<<0)
1260 #define BNX_PCI_ID_VAL4_CAP_ENA_6			 (6L<<0)
1261 #define BNX_PCI_ID_VAL4_CAP_ENA_7			 (7L<<0)
1262 #define BNX_PCI_ID_VAL4_CAP_ENA_8			 (8L<<0)
1263 #define BNX_PCI_ID_VAL4_CAP_ENA_9			 (9L<<0)
1264 #define BNX_PCI_ID_VAL4_CAP_ENA_10			 (10L<<0)
1265 #define BNX_PCI_ID_VAL4_CAP_ENA_11			 (11L<<0)
1266 #define BNX_PCI_ID_VAL4_CAP_ENA_12			 (12L<<0)
1267 #define BNX_PCI_ID_VAL4_CAP_ENA_13			 (13L<<0)
1268 #define BNX_PCI_ID_VAL4_CAP_ENA_14			 (14L<<0)
1269 #define BNX_PCI_ID_VAL4_CAP_ENA_15			 (15L<<0)
1271 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_0			 (0L<<6)
1272 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_1			 (1L<<6)
1273 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_2			 (2L<<6)
1274 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_3			 (3L<<6)
1277 #define BNX_PCI_ID_VAL4_MSI_ENABLE			 (1L<<15)
1278 #define BNX_PCI_ID_VAL4_MAX_64_ADVERTIZE		 (1L<<16)
1279 #define BNX_PCI_ID_VAL4_MAX_133_ADVERTIZE		 (1L<<17)
1285 #define BNX_PCI_ID_VAL5_D1_SUPPORT			 (1L<<0)
1286 #define BNX_PCI_ID_VAL5_D2_SUPPORT			 (1L<<1)
1287 #define BNX_PCI_ID_VAL5_PME_IN_D0			 (1L<<2)
1288 #define BNX_PCI_ID_VAL5_PME_IN_D1			 (1L<<3)
1289 #define BNX_PCI_ID_VAL5_PME_IN_D2			 (1L<<4)
1290 #define BNX_PCI_ID_VAL5_PME_IN_D3_HOT			 (1L<<5)
1293 #define BNX_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP		 (1L<<8)
1294 #define BNX_PCI_PCIX_EXTENDED_STATUS_LONG_BURST	 (1L<<9)
1315 #define BNX_MISC_COMMAND_ENABLE_ALL			 (1L<<0)
1316 #define BNX_MISC_COMMAND_DISABLE_ALL			 (1L<<1)
1317 #define BNX_MISC_COMMAND_SW_RESET			 (1L<<4)
1318 #define BNX_MISC_COMMAND_POR_RESET			 (1L<<5)
1319 #define BNX_MISC_COMMAND_HD_RESET			 (1L<<6)
1320 #define BNX_MISC_COMMAND_CMN_SW_RESET			 (1L<<7)
1321 #define BNX_MISC_COMMAND_PAR_ERROR			 (1L<<8)
1322 #define BNX_MISC_COMMAND_CS16_ERR			 (1L<<9)
1325 #define BNX_MISC_COMMAND_POWERDOWN_EVENT		 (1L<<23)
1326 #define BNX_MISC_COMMAND_SW_SHUTDOWN			 (1L<<24)
1327 #define BNX_MISC_COMMAND_SHUTDOWN_EN			 (1L<<25)
1328 #define BNX_MISC_COMMAND_DINTEG_ATTN_EN			 (1L<<26)
1329 #define BNX_MISC_COMMAND_PCIE_LINK_IN_L23		 (1L<<27)
1330 #define BNX_MISC_COMMAND_PCIE_DIS			 (1L<<28)
1333 #define BNX_MISC_CFG_PCI_GRC_TMOUT			 (1L<<0)
1335 #define BNX_MISC_CFG_NVM_WR_EN_PROTECT			 (0L<<1)
1336 #define BNX_MISC_CFG_NVM_WR_EN_PCI			 (1L<<1)
1337 #define BNX_MISC_CFG_NVM_WR_EN_ALLOW			 (2L<<1)
1338 #define BNX_MISC_CFG_NVM_WR_EN_ALLOW2			 (3L<<1)
1339 #define BNX_MISC_CFG_BIST_EN				 (1L<<3)
1340 #define BNX_MISC_CFG_CK25_OUT_ALT_SRC			 (1L<<4)
1341 #define BNX_MISC_CFG_BYPASS_BSCAN			 (1L<<5)
1342 #define BNX_MISC_CFG_BYPASS_EJTAG			 (1L<<6)
1343 #define BNX_MISC_CFG_CLK_CTL_OVERRIDE			 (1L<<7)
1345 #define BNX_MISC_CFG_LEDMODE_MAC			 (0L<<8)
1346 #define BNX_MISC_CFG_LEDMODE_GPHY1			 (1L<<8)
1347 #define BNX_MISC_CFG_LEDMODE_GPHY2			 (2L<<8)
1356 #define BNX_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1357 #define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1358 #define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1359 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1360 #define BNX_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE	 (1L<<4)
1361 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1362 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1363 #define BNX_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1364 #define BNX_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1365 #define BNX_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE	 (1L<<9)
1366 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1367 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1368 #define BNX_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE	 (1L<<12)
1369 #define BNX_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1370 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1371 #define BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE	 (1L<<15)
1372 #define BNX_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1373 #define BNX_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE	 (1L<<17)
1374 #define BNX_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE	 (1L<<18)
1375 #define BNX_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1376 #define BNX_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1377 #define BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE	 (1L<<21)
1378 #define BNX_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1379 #define BNX_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1380 #define BNX_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1381 #define BNX_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE	 (1L<<25)
1382 #define BNX_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1383 #define BNX_MISC_ENABLE_STATUS_BITS_UMP_ENABLE		 (1L<<27)
1386 #define BNX_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1387 #define BNX_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1388 #define BNX_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1389 #define BNX_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1390 #define BNX_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE		 (1L<<4)
1391 #define BNX_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1392 #define BNX_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1393 #define BNX_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1394 #define BNX_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1395 #define BNX_MISC_ENABLE_SET_BITS_EMAC_ENABLE		 (1L<<9)
1396 #define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1397 #define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1398 #define BNX_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE	 (1L<<12)
1399 #define BNX_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1400 #define BNX_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1401 #define BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE		 (1L<<15)
1402 #define BNX_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1403 #define BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE		 (1L<<17)
1404 #define BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE	 (1L<<18)
1405 #define BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1406 #define BNX_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1407 #define BNX_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE	 (1L<<21)
1408 #define BNX_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1409 #define BNX_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1410 #define BNX_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1411 #define BNX_MISC_ENABLE_SET_BITS_TIMER_ENABLE		 (1L<<25)
1412 #define BNX_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1413 #define BNX_MISC_ENABLE_SET_BITS_UMP_ENABLE		 (1L<<27)
1419 #define BNX_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1420 #define BNX_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1421 #define BNX_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1422 #define BNX_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1423 #define BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE		 (1L<<4)
1424 #define BNX_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1425 #define BNX_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1426 #define BNX_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1427 #define BNX_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1428 #define BNX_MISC_ENABLE_CLR_BITS_EMAC_ENABLE		 (1L<<9)
1429 #define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1430 #define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1431 #define BNX_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE	 (1L<<12)
1432 #define BNX_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1433 #define BNX_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1434 #define BNX_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE		 (1L<<15)
1435 #define BNX_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1436 #define BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE		 (1L<<17)
1437 #define BNX_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE	 (1L<<18)
1438 #define BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1439 #define BNX_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1440 #define BNX_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE	 (1L<<21)
1441 #define BNX_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1442 #define BNX_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1443 #define BNX_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1444 #define BNX_MISC_ENABLE_CLR_BITS_TIMER_ENABLE		 (1L<<25)
1445 #define BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1446 #define BNX_MISC_ENABLE_CLR_BITS_UMP_ENABLE		 (1L<<27)
1450 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
1451 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
1452 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
1453 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
1454 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
1455 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
1456 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
1457 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)
1459 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE	 (1L<<6)
1460 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT	 (1L<<7)
1462 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)
1463 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12	 (1L<<8)
1464 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6	 (2L<<8)
1465 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62	 (4L<<8)
1466 #define BNX_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD		 (1L<<11)
1468 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)
1469 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)
1470 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)
1471 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)
1472 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)
1473 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP	 (1L<<16)
1474 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP	 (1L<<17)
1475 #define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED_18	 (1L<<18)
1476 #define BNX_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET	 (1L<<19)
1495 #define BNX_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1496 #define BNX_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1497 #define BNX_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1498 #define BNX_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1499 #define BNX_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE		 (1L<<4)
1500 #define BNX_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1501 #define BNX_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1502 #define BNX_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1503 #define BNX_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1504 #define BNX_MISC_LFSR_MASK_BITS_EMAC_ENABLE		 (1L<<9)
1505 #define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1506 #define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1507 #define BNX_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE		 (1L<<12)
1508 #define BNX_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1509 #define BNX_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1510 #define BNX_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE		 (1L<<15)
1511 #define BNX_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1512 #define BNX_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE		 (1L<<17)
1513 #define BNX_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE	 (1L<<18)
1514 #define BNX_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1515 #define BNX_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1516 #define BNX_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE		 (1L<<21)
1517 #define BNX_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1518 #define BNX_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1519 #define BNX_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1520 #define BNX_MISC_LFSR_MASK_BITS_TIMER_ENABLE		 (1L<<25)
1521 #define BNX_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1522 #define BNX_MISC_LFSR_MASK_BITS_UMP_ENABLE		 (1L<<27)
1580 #define BNX_MISC_PRBS_CONTROL_EN			 (1L<<0)
1581 #define BNX_MISC_PRBS_CONTROL_RSTB			 (1L<<1)
1582 #define BNX_MISC_PRBS_CONTROL_INV			 (1L<<2)
1583 #define BNX_MISC_PRBS_CONTROL_ERR_CLR			 (1L<<3)
1585 #define BNX_MISC_PRBS_CONTROL_ORDER_7TH		 (0L<<4)
1586 #define BNX_MISC_PRBS_CONTROL_ORDER_15TH		 (1L<<4)
1587 #define BNX_MISC_PRBS_CONTROL_ORDER_23RD		 (2L<<4)
1588 #define BNX_MISC_PRBS_CONTROL_ORDER_31ST		 (3L<<4)
1591 #define BNX_MISC_PRBS_STATUS_LOCK			 (1L<<0)
1592 #define BNX_MISC_PRBS_STATUS_STKY			 (1L<<1)
1597 #define BNX_MISC_SM_ASF_CONTROL_ASF_RST		 (1L<<0)
1598 #define BNX_MISC_SM_ASF_CONTROL_TSC_EN			 (1L<<1)
1599 #define BNX_MISC_SM_ASF_CONTROL_WG_TO			 (1L<<2)
1600 #define BNX_MISC_SM_ASF_CONTROL_HB_TO			 (1L<<3)
1601 #define BNX_MISC_SM_ASF_CONTROL_PA_TO			 (1L<<4)
1602 #define BNX_MISC_SM_ASF_CONTROL_PL_TO			 (1L<<5)
1603 #define BNX_MISC_SM_ASF_CONTROL_RT_TO			 (1L<<6)
1604 #define BNX_MISC_SM_ASF_CONTROL_SMB_EVENT		 (1L<<7)
1606 #define BNX_MISC_SM_ASF_CONTROL_SMB_EN			 (1L<<12)
1607 #define BNX_MISC_SM_ASF_CONTROL_SMB_BB_EN		 (1L<<13)
1608 #define BNX_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT	 (1L<<14)
1609 #define BNX_MISC_SM_ASF_CONTROL_SMB_AUTOREAD		 (1L<<15)
1612 #define BNX_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0	 (1L<<30)
1613 #define BNX_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN		 (1L<<31)
1617 #define BNX_MISC_SMB_IN_RDY				 (1L<<8)
1618 #define BNX_MISC_SMB_IN_DONE				 (1L<<9)
1619 #define BNX_MISC_SMB_IN_FIRSTBYTE			 (1L<<10)
1629 #define BNX_MISC_SMB_OUT_RDY				 (1L<<8)
1630 #define BNX_MISC_SMB_OUT_START				 (1L<<9)
1631 #define BNX_MISC_SMB_OUT_LAST				 (1L<<10)
1632 #define BNX_MISC_SMB_OUT_ACC_TYPE			 (1L<<11)
1633 #define BNX_MISC_SMB_OUT_ENB_PEC			 (1L<<12)
1634 #define BNX_MISC_SMB_OUT_GET_RX_LEN			 (1L<<13)
1637 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_OK		 (0L<<20)
1638 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK	 (1L<<20)
1639 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK	 (9L<<20)
1640 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW		 (2L<<20)
1641 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_STOP		 (3L<<20)
1642 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT	 (4L<<20)
1643 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST	 (5L<<20)
1646 #define BNX_MISC_SMB_OUT_SMB_OUT_SLAVEMODE		 (1L<<24)
1647 #define BNX_MISC_SMB_OUT_SMB_OUT_DAT_EN		 (1L<<25)
1648 #define BNX_MISC_SMB_OUT_SMB_OUT_DAT_IN		 (1L<<26)
1649 #define BNX_MISC_SMB_OUT_SMB_OUT_CLK_EN		 (1L<<27)
1650 #define BNX_MISC_SMB_OUT_SMB_OUT_CLK_IN		 (1L<<28)
1671 #define BNX_MISC_PERR_ENA0_COM_MISC_CTXC		 (1L<<0)
1672 #define BNX_MISC_PERR_ENA0_COM_MISC_REGF		 (1L<<1)
1673 #define BNX_MISC_PERR_ENA0_COM_MISC_SCPAD		 (1L<<2)
1674 #define BNX_MISC_PERR_ENA0_CP_MISC_CTXC		 (1L<<3)
1675 #define BNX_MISC_PERR_ENA0_CP_MISC_REGF		 (1L<<4)
1676 #define BNX_MISC_PERR_ENA0_CP_MISC_SCPAD		 (1L<<5)
1677 #define BNX_MISC_PERR_ENA0_CS_MISC_TMEM		 (1L<<6)
1678 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM0		 (1L<<7)
1679 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM1		 (1L<<8)
1680 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM2		 (1L<<9)
1681 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM3		 (1L<<10)
1682 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM4		 (1L<<11)
1683 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM5		 (1L<<12)
1684 #define BNX_MISC_PERR_ENA0_CTX_MISC_PGTBL		 (1L<<13)
1685 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR0		 (1L<<14)
1686 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR1		 (1L<<15)
1687 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR2		 (1L<<16)
1688 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR3		 (1L<<17)
1689 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR4		 (1L<<18)
1690 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW0		 (1L<<19)
1691 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW1		 (1L<<20)
1692 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW2		 (1L<<21)
1693 #define BNX_MISC_PERR_ENA0_HC_MISC_DMA			 (1L<<22)
1694 #define BNX_MISC_PERR_ENA0_MCP_MISC_REGF		 (1L<<23)
1695 #define BNX_MISC_PERR_ENA0_MCP_MISC_SCPAD		 (1L<<24)
1696 #define BNX_MISC_PERR_ENA0_MQ_MISC_CTX			 (1L<<25)
1697 #define BNX_MISC_PERR_ENA0_RBDC_MISC			 (1L<<26)
1698 #define BNX_MISC_PERR_ENA0_RBUF_MISC_MB		 (1L<<27)
1699 #define BNX_MISC_PERR_ENA0_RBUF_MISC_PTR		 (1L<<28)
1700 #define BNX_MISC_PERR_ENA0_RDE_MISC_RPC		 (1L<<29)
1701 #define BNX_MISC_PERR_ENA0_RDE_MISC_RPM		 (1L<<30)
1702 #define BNX_MISC_PERR_ENA0_RV2P_MISC_CB0REGS		 (1L<<31)
1705 #define BNX_MISC_PERR_ENA1_RV2P_MISC_CB1REGS		 (1L<<0)
1706 #define BNX_MISC_PERR_ENA1_RV2P_MISC_P1IRAM		 (1L<<1)
1707 #define BNX_MISC_PERR_ENA1_RV2P_MISC_P2IRAM		 (1L<<2)
1708 #define BNX_MISC_PERR_ENA1_RXP_MISC_CTXC		 (1L<<3)
1709 #define BNX_MISC_PERR_ENA1_RXP_MISC_REGF		 (1L<<4)
1710 #define BNX_MISC_PERR_ENA1_RXP_MISC_SCPAD		 (1L<<5)
1711 #define BNX_MISC_PERR_ENA1_RXP_MISC_RBUFC		 (1L<<6)
1712 #define BNX_MISC_PERR_ENA1_TBDC_MISC			 (1L<<7)
1713 #define BNX_MISC_PERR_ENA1_TDMA_MISC			 (1L<<8)
1714 #define BNX_MISC_PERR_ENA1_THBUF_MISC_MB0		 (1L<<9)
1715 #define BNX_MISC_PERR_ENA1_THBUF_MISC_MB1		 (1L<<10)
1716 #define BNX_MISC_PERR_ENA1_TPAT_MISC_REGF		 (1L<<11)
1717 #define BNX_MISC_PERR_ENA1_TPAT_MISC_SCPAD		 (1L<<12)
1718 #define BNX_MISC_PERR_ENA1_TPBUF_MISC_MB		 (1L<<13)
1719 #define BNX_MISC_PERR_ENA1_TSCH_MISC_LR		 (1L<<14)
1720 #define BNX_MISC_PERR_ENA1_TXP_MISC_CTXC		 (1L<<15)
1721 #define BNX_MISC_PERR_ENA1_TXP_MISC_REGF		 (1L<<16)
1722 #define BNX_MISC_PERR_ENA1_TXP_MISC_SCPAD		 (1L<<17)
1723 #define BNX_MISC_PERR_ENA1_UMP_MISC_FIORX		 (1L<<18)
1724 #define BNX_MISC_PERR_ENA1_UMP_MISC_FIOTX		 (1L<<19)
1725 #define BNX_MISC_PERR_ENA1_UMP_MISC_RX			 (1L<<20)
1726 #define BNX_MISC_PERR_ENA1_UMP_MISC_TX			 (1L<<21)
1727 #define BNX_MISC_PERR_ENA1_RDMAQ_MISC			 (1L<<22)
1728 #define BNX_MISC_PERR_ENA1_CSQ_MISC			 (1L<<23)
1729 #define BNX_MISC_PERR_ENA1_CPQ_MISC			 (1L<<24)
1730 #define BNX_MISC_PERR_ENA1_MCPQ_MISC			 (1L<<25)
1731 #define BNX_MISC_PERR_ENA1_RV2PMQ_MISC			 (1L<<26)
1732 #define BNX_MISC_PERR_ENA1_RV2PPQ_MISC			 (1L<<27)
1733 #define BNX_MISC_PERR_ENA1_RV2PTQ_MISC			 (1L<<28)
1734 #define BNX_MISC_PERR_ENA1_RXPQ_MISC			 (1L<<29)
1735 #define BNX_MISC_PERR_ENA1_RXPCQ_MISC			 (1L<<30)
1736 #define BNX_MISC_PERR_ENA1_RLUPQ_MISC			 (1L<<31)
1739 #define BNX_MISC_PERR_ENA2_COMQ_MISC			 (1L<<0)
1740 #define BNX_MISC_PERR_ENA2_COMXQ_MISC			 (1L<<1)
1741 #define BNX_MISC_PERR_ENA2_COMTQ_MISC			 (1L<<2)
1742 #define BNX_MISC_PERR_ENA2_TSCHQ_MISC			 (1L<<3)
1743 #define BNX_MISC_PERR_ENA2_TBDRQ_MISC			 (1L<<4)
1744 #define BNX_MISC_PERR_ENA2_TXPQ_MISC			 (1L<<5)
1745 #define BNX_MISC_PERR_ENA2_TDMAQ_MISC			 (1L<<6)
1746 #define BNX_MISC_PERR_ENA2_TPATQ_MISC			 (1L<<7)
1747 #define BNX_MISC_PERR_ENA2_TASQ_MISC			 (1L<<8)
1761 #define BNX_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS	 (1L<<0)
1762 #define BNX_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ		 (1L<<1)
1763 #define BNX_MISC_NEW_CORE_CTL_DMA_ENABLE		 (1L<<16)
1769 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_X		 (0L<<0)
1770 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C		 (3L<<0)
1771 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S		 (12L<<0)
1773 #define BNX_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN		 (1L<<11)
1774 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET	 (1L<<12)
1775 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET	 (1L<<13)
1776 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET		 (1L<<14)
1777 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET		 (1L<<15)
1778 #define BNX_MISC_DUAL_MEDIA_CTRL_LCPLL_RST		 (1L<<16)
1779 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES1_RST		 (1L<<17)
1780 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES0_RST		 (1L<<18)
1781 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY1_RST		 (1L<<19)
1782 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY0_RST		 (1L<<20)
1784 #define BNX_MISC_DUAL_MEDIA_CTRL_PORT_SWAP		 (1L<<24)
1785 #define BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE	 (1L<<25)
1787 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ	 (1L<<26)
1788 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ	 (2L<<26)
1789 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ	 (4L<<26)
1790 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ	 (8L<<26)
1800 #define BNX_NVM_COMMAND_RST				 (1L<<0)
1801 #define BNX_NVM_COMMAND_DONE				 (1L<<3)
1802 #define BNX_NVM_COMMAND_DOIT				 (1L<<4)
1803 #define BNX_NVM_COMMAND_WR				 (1L<<5)
1804 #define BNX_NVM_COMMAND_ERASE				 (1L<<6)
1805 #define BNX_NVM_COMMAND_FIRST				 (1L<<7)
1806 #define BNX_NVM_COMMAND_LAST				 (1L<<8)
1807 #define BNX_NVM_COMMAND_WREN				 (1L<<16)
1808 #define BNX_NVM_COMMAND_WRDI				 (1L<<17)
1809 #define BNX_NVM_COMMAND_EWSR				 (1L<<18)
1810 #define BNX_NVM_COMMAND_WRSR				 (1L<<19)
1819 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG		 (0L<<0)
1820 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_EECLK		 (1L<<0)
1821 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_EEDATA		 (2L<<0)
1822 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SCLK		 (4L<<0)
1823 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_CS_B		 (8L<<0)
1824 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SO		 (16L<<0)
1825 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SI		 (32L<<0)
1829 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG		 (0L<<0)
1830 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_EECLK		 (1L<<0)
1831 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_EEDATA		 (2L<<0)
1832 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SCLK		 (4L<<0)
1833 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_CS_B		 (8L<<0)
1834 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SO			 (16L<<0)
1835 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SI			 (32L<<0)
1839 #define BNX_NVM_READ_NVM_READ_VALUE_BIT_BANG		 (0L<<0)
1840 #define BNX_NVM_READ_NVM_READ_VALUE_EECLK		 (1L<<0)
1841 #define BNX_NVM_READ_NVM_READ_VALUE_EEDATA		 (2L<<0)
1842 #define BNX_NVM_READ_NVM_READ_VALUE_SCLK		 (4L<<0)
1843 #define BNX_NVM_READ_NVM_READ_VALUE_CS_B		 (8L<<0)
1844 #define BNX_NVM_READ_NVM_READ_VALUE_SO			 (16L<<0)
1845 #define BNX_NVM_READ_NVM_READ_VALUE_SI			 (32L<<0)
1848 #define BNX_NVM_CFG1_FLASH_MODE			 (1L<<0)
1849 #define BNX_NVM_CFG1_BUFFER_MODE			 (1L<<1)
1850 #define BNX_NVM_CFG1_PASS_MODE				 (1L<<2)
1851 #define BNX_NVM_CFG1_BITBANG_MODE			 (1L<<3)
1853 #define BNX_NVM_CFG1_STATUS_BIT_FLASH_RDY		 (0L<<4)
1854 #define BNX_NVM_CFG1_STATUS_BIT_BUFFER_RDY		 (7L<<4)
1857 #define BNX_NVM_CFG1_PROTECT_MODE			 (1L<<24)
1858 #define BNX_NVM_CFG1_FLASH_SIZE			 (1L<<25)
1859 #define BNX_NVM_CFG1_COMPAT_BYPASSS			 (1L<<31)
1873 #define BNX_NVM_SW_ARB_ARB_REQ_SET0			 (1L<<0)
1874 #define BNX_NVM_SW_ARB_ARB_REQ_SET1			 (1L<<1)
1875 #define BNX_NVM_SW_ARB_ARB_REQ_SET2			 (1L<<2)
1876 #define BNX_NVM_SW_ARB_ARB_REQ_SET3			 (1L<<3)
1877 #define BNX_NVM_SW_ARB_ARB_REQ_CLR0			 (1L<<4)
1878 #define BNX_NVM_SW_ARB_ARB_REQ_CLR1			 (1L<<5)
1879 #define BNX_NVM_SW_ARB_ARB_REQ_CLR2			 (1L<<6)
1880 #define BNX_NVM_SW_ARB_ARB_REQ_CLR3			 (1L<<7)
1881 #define BNX_NVM_SW_ARB_ARB_ARB0			 (1L<<8)
1882 #define BNX_NVM_SW_ARB_ARB_ARB1			 (1L<<9)
1883 #define BNX_NVM_SW_ARB_ARB_ARB2			 (1L<<10)
1884 #define BNX_NVM_SW_ARB_ARB_ARB3			 (1L<<11)
1885 #define BNX_NVM_SW_ARB_REQ0				 (1L<<12)
1886 #define BNX_NVM_SW_ARB_REQ1				 (1L<<13)
1887 #define BNX_NVM_SW_ARB_REQ2				 (1L<<14)
1888 #define BNX_NVM_SW_ARB_REQ3				 (1L<<15)
1891 #define BNX_NVM_ACCESS_ENABLE_EN			 (1L<<0)
1892 #define BNX_NVM_ACCESS_ENABLE_WR_EN			 (1L<<1)
1906 #define BNX_DMA_COMMAND_ENABLE				 (1L<<0)
1909 #define BNX_DMA_STATUS_PAR_ERROR_STATE			 (1L<<0)
1910 #define BNX_DMA_STATUS_READ_TRANSFERS_STAT		 (1L<<16)
1911 #define BNX_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT	 (1L<<17)
1912 #define BNX_DMA_STATUS_BIG_READ_TRANSFERS_STAT		 (1L<<18)
1913 #define BNX_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT	 (1L<<19)
1914 #define BNX_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT	 (1L<<20)
1915 #define BNX_DMA_STATUS_WRITE_TRANSFERS_STAT		 (1L<<21)
1916 #define BNX_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT	 (1L<<22)
1917 #define BNX_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT	 (1L<<23)
1918 #define BNX_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT	 (1L<<24)
1919 #define BNX_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT	 (1L<<25)
1922 #define BNX_DMA_CONFIG_DATA_BYTE_SWAP			 (1L<<0)
1923 #define BNX_DMA_CONFIG_DATA_WORD_SWAP			 (1L<<1)
1924 #define BNX_DMA_CONFIG_CNTL_BYTE_SWAP			 (1L<<4)
1925 #define BNX_DMA_CONFIG_CNTL_WORD_SWAP			 (1L<<5)
1926 #define BNX_DMA_CONFIG_ONE_DMA				 (1L<<6)
1927 #define BNX_DMA_CONFIG_CNTL_TWO_DMA			 (1L<<7)
1928 #define BNX_DMA_CONFIG_CNTL_FPGA_MODE			 (1L<<8)
1929 #define BNX_DMA_CONFIG_CNTL_PING_PONG_DMA		 (1L<<10)
1930 #define BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY		 (1L<<11)
1934 #define BNX_DMA_CONFIG_PCI_FAST_CLK_CMP		 (1L<<23)
1949 #define BNX_DMA_RCHAN_STAT_PAR_ERR_0			 (1L<<3)
1951 #define BNX_DMA_RCHAN_STAT_PAR_ERR_1			 (1L<<7)
1953 #define BNX_DMA_RCHAN_STAT_PAR_ERR_2			 (1L<<11)
1955 #define BNX_DMA_RCHAN_STAT_PAR_ERR_3			 (1L<<15)
1957 #define BNX_DMA_RCHAN_STAT_PAR_ERR_4			 (1L<<19)
1959 #define BNX_DMA_RCHAN_STAT_PAR_ERR_5			 (1L<<23)
1961 #define BNX_DMA_RCHAN_STAT_PAR_ERR_6			 (1L<<27)
1963 #define BNX_DMA_RCHAN_STAT_PAR_ERR_7			 (1L<<31)
1967 #define BNX_DMA_WCHAN_STAT_PAR_ERR_0			 (1L<<3)
1969 #define BNX_DMA_WCHAN_STAT_PAR_ERR_1			 (1L<<7)
1971 #define BNX_DMA_WCHAN_STAT_PAR_ERR_2			 (1L<<11)
1973 #define BNX_DMA_WCHAN_STAT_PAR_ERR_3			 (1L<<15)
1975 #define BNX_DMA_WCHAN_STAT_PAR_ERR_4			 (1L<<19)
1977 #define BNX_DMA_WCHAN_STAT_PAR_ERR_5			 (1L<<23)
1979 #define BNX_DMA_WCHAN_STAT_PAR_ERR_6			 (1L<<27)
1981 #define BNX_DMA_WCHAN_STAT_PAR_ERR_7			 (1L<<31)
2011 #define BNX_DMA_RCHAN_STAT_02_WORD_SWAP		 (1L<<16)
2012 #define BNX_DMA_RCHAN_STAT_02_BYTE_SWAP		 (1L<<17)
2013 #define BNX_DMA_RCHAN_STAT_02_PRIORITY_LVL		 (1L<<18)
2044 #define BNX_DMA_WCHAN_STAT_02_WORD_SWAP		 (1L<<16)
2045 #define BNX_DMA_WCHAN_STAT_02_BYTE_SWAP		 (1L<<17)
2046 #define BNX_DMA_WCHAN_STAT_02_PRIORITY_LVL		 (1L<<18)
2085 #define BNX_DMA_FUSE_CTRL0_CMD_PWRUP_DONE		 (1L<<0)
2086 #define BNX_DMA_FUSE_CTRL0_CMD_SHIFT_DONE		 (1L<<1)
2087 #define BNX_DMA_FUSE_CTRL0_CMD_SHIFT			 (1L<<2)
2088 #define BNX_DMA_FUSE_CTRL0_CMD_LOAD			 (1L<<3)
2093 #define BNX_DMA_FUSE_CTRL1_CMD_PWRUP_DONE		 (1L<<0)
2094 #define BNX_DMA_FUSE_CTRL1_CMD_SHIFT_DONE		 (1L<<1)
2095 #define BNX_DMA_FUSE_CTRL1_CMD_SHIFT			 (1L<<2)
2096 #define BNX_DMA_FUSE_CTRL1_CMD_LOAD			 (1L<<3)
2101 #define BNX_DMA_FUSE_CTRL2_CMD_PWRUP_DONE		 (1L<<0)
2102 #define BNX_DMA_FUSE_CTRL2_CMD_SHIFT_DONE		 (1L<<1)
2103 #define BNX_DMA_FUSE_CTRL2_CMD_SHIFT			 (1L<<2)
2104 #define BNX_DMA_FUSE_CTRL2_CMD_LOAD			 (1L<<3)
2115 #define BNX_CTX_COMMAND_ENABLED				 (1L<<0)
2116 #define BNX_CTX_COMMAND_DISABLE_USAGE_CNT		 (1L<<1)
2117 #define BNX_CTX_COMMAND_DISABLE_PLRU			 (1L<<2)
2118 #define BNX_CTX_COMMAND_DISABLE_COMBINE_READ		 (1L<<3)
2120 #define BNX_CTX_COMMAND_MEM_INIT			 (1L<<13)
2122 #define BNX_CTX_COMMAND_PAGE_SIZE_256			 (0L<<16)
2123 #define BNX_CTX_COMMAND_PAGE_SIZE_512			 (1L<<16)
2124 #define BNX_CTX_COMMAND_PAGE_SIZE_1K			 (2L<<16)
2125 #define BNX_CTX_COMMAND_PAGE_SIZE_2K			 (3L<<16)
2126 #define BNX_CTX_COMMAND_PAGE_SIZE_4K			 (4L<<16)
2127 #define BNX_CTX_COMMAND_PAGE_SIZE_8K			 (5L<<16)
2128 #define BNX_CTX_COMMAND_PAGE_SIZE_16K			 (6L<<16)
2129 #define BNX_CTX_COMMAND_PAGE_SIZE_32K			 (7L<<16)
2130 #define BNX_CTX_COMMAND_PAGE_SIZE_64K			 (8L<<16)
2131 #define BNX_CTX_COMMAND_PAGE_SIZE_128K			 (9L<<16)
2132 #define BNX_CTX_COMMAND_PAGE_SIZE_256K			 (10L<<16)
2133 #define BNX_CTX_COMMAND_PAGE_SIZE_512K			 (11L<<16)
2134 #define BNX_CTX_COMMAND_PAGE_SIZE_1M			 (12L<<16)
2137 #define BNX_CTX_STATUS_LOCK_WAIT			 (1L<<0)
2138 #define BNX_CTX_STATUS_READ_STAT			 (1L<<16)
2139 #define BNX_CTX_STATUS_WRITE_STAT			 (1L<<17)
2140 #define BNX_CTX_STATUS_ACC_STALL_STAT			 (1L<<18)
2141 #define BNX_CTX_STATUS_LOCK_STALL_STAT			 (1L<<19)
2161 #define BNX_CTX_LOCK_GRANTED				 (1L<<26)
2166 #define BNX_CTX_LOCK_STATUS				 (1L<<30)
2167 #define BNX_CTX_LOCK_REQ				 (1L<<31)
2172 #define BNX_CTX_CTX_CTRL_NO_RAM_ACC			(1L<<23)
2174 #define BNX_CTX_CTX_CTRL_ATTR				(1L<<26)
2175 #define BNX_CTX_CTX_CTRL_WRITE_REQ			(1L<<30)
2176 #define BNX_CTX_CTX_CTRL_READ_REQ			(1L<<31)
2197 #define BNX_CTX_CHNL_LOCK_STATUS_0_MODE		 (1L<<16)
2211 #define BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ		 (1L<<30)
2212 #define BNX_CTX_HOST_PAGE_TBL_CTRL_READ_REQ		 (1L<<31)
2215 #define BNX_CTX_HOST_PAGE_TBL_DATA0_VALID		 (1L<<0)
2225 #define BNX_EMAC_MODE_RESET				 (1L<<0)
2226 #define BNX_EMAC_MODE_HALF_DUPLEX			 (1L<<1)
2228 #define BNX_EMAC_MODE_PORT_NONE			 (0L<<2)
2229 #define BNX_EMAC_MODE_PORT_MII				 (1L<<2)
2230 #define BNX_EMAC_MODE_PORT_GMII			 (2L<<2)
2231 #define BNX_EMAC_MODE_PORT_MII_10			 (3L<<2)
2232 #define BNX_EMAC_MODE_MAC_LOOP				 (1L<<4)
2233 #define BNX_EMAC_MODE_25G				 (1L<<5)
2234 #define BNX_EMAC_MODE_TAGGED_MAC_CTL			 (1L<<7)
2235 #define BNX_EMAC_MODE_TX_BURST				 (1L<<8)
2236 #define BNX_EMAC_MODE_MAX_DEFER_DROP_ENA		 (1L<<9)
2237 #define BNX_EMAC_MODE_EXT_LINK_POL			 (1L<<10)
2238 #define BNX_EMAC_MODE_FORCE_LINK			 (1L<<11)
2239 #define BNX_EMAC_MODE_MPKT				 (1L<<18)
2240 #define BNX_EMAC_MODE_MPKT_RCVD			 (1L<<19)
2241 #define BNX_EMAC_MODE_ACPI_RCVD			 (1L<<20)
2244 #define BNX_EMAC_STATUS_LINK				 (1L<<11)
2245 #define BNX_EMAC_STATUS_LINK_CHANGE			 (1L<<12)
2246 #define BNX_EMAC_STATUS_MI_COMPLETE			 (1L<<22)
2247 #define BNX_EMAC_STATUS_MI_INT				 (1L<<23)
2248 #define BNX_EMAC_STATUS_AP_ERROR			 (1L<<24)
2249 #define BNX_EMAC_STATUS_PARITY_ERROR_STATE		 (1L<<31)
2252 #define BNX_EMAC_ATTENTION_ENA_LINK			 (1L<<11)
2253 #define BNX_EMAC_ATTENTION_ENA_MI_COMPLETE		 (1L<<22)
2254 #define BNX_EMAC_ATTENTION_ENA_MI_INT			 (1L<<23)
2255 #define BNX_EMAC_ATTENTION_ENA_AP_ERROR		 (1L<<24)
2258 #define BNX_EMAC_LED_OVERRIDE				 (1L<<0)
2259 #define BNX_EMAC_LED_1000MB_OVERRIDE			 (1L<<1)
2260 #define BNX_EMAC_LED_100MB_OVERRIDE			 (1L<<2)
2261 #define BNX_EMAC_LED_10MB_OVERRIDE			 (1L<<3)
2262 #define BNX_EMAC_LED_TRAFFIC_OVERRIDE			 (1L<<4)
2263 #define BNX_EMAC_LED_BLNK_TRAFFIC			 (1L<<5)
2264 #define BNX_EMAC_LED_TRAFFIC				 (1L<<6)
2265 #define BNX_EMAC_LED_1000MB				 (1L<<7)
2266 #define BNX_EMAC_LED_100MB				 (1L<<8)
2267 #define BNX_EMAC_LED_10MB				 (1L<<9)
2268 #define BNX_EMAC_LED_TRAFFIC_STAT			 (1L<<10)
2270 #define BNX_EMAC_LED_BLNK_RATE_ENA			 (1L<<31)
2309 #define BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA			 (1L<<31)
2314 #define BNX_EMAC_SERDES_CNTL_RXCKSEL			 (1L<<6)
2316 #define BNX_EMAC_SERDES_CNTL_BGMAX			 (1L<<10)
2317 #define BNX_EMAC_SERDES_CNTL_BGMIN			 (1L<<11)
2318 #define BNX_EMAC_SERDES_CNTL_TXMODE			 (1L<<12)
2319 #define BNX_EMAC_SERDES_CNTL_TXEDGE			 (1L<<13)
2320 #define BNX_EMAC_SERDES_CNTL_SERDES_MODE		 (1L<<14)
2321 #define BNX_EMAC_SERDES_CNTL_PLLTEST			 (1L<<15)
2322 #define BNX_EMAC_SERDES_CNTL_CDET_EN			 (1L<<16)
2323 #define BNX_EMAC_SERDES_CNTL_TBI_LBK			 (1L<<17)
2324 #define BNX_EMAC_SERDES_CNTL_REMOTE_LBK		 (1L<<18)
2325 #define BNX_EMAC_SERDES_CNTL_REV_PHASE			 (1L<<19)
2331 #define BNX_EMAC_SERDES_STATUS_COMMA_DET		 (1L<<8)
2338 #define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0		 (0L<<26)
2339 #define BNX_EMAC_MDIO_COMM_COMMAND_WRITE		 (1L<<26)
2340 #define BNX_EMAC_MDIO_COMM_COMMAND_READ		 (2L<<26)
2341 #define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3		 (3L<<26)
2342 #define BNX_EMAC_MDIO_COMM_FAIL			 (1L<<28)
2343 #define BNX_EMAC_MDIO_COMM_START_BUSY			 (1L<<29)
2344 #define BNX_EMAC_MDIO_COMM_DISEXT			 (1L<<30)
2347 #define BNX_EMAC_MDIO_STATUS_LINK			 (1L<<0)
2348 #define BNX_EMAC_MDIO_STATUS_10MB			 (1L<<1)
2351 #define BNX_EMAC_MDIO_MODE_SHORT_PREAMBLE		 (1L<<1)
2352 #define BNX_EMAC_MDIO_MODE_AUTO_POLL			 (1L<<4)
2353 #define BNX_EMAC_MDIO_MODE_BIT_BANG			 (1L<<8)
2354 #define BNX_EMAC_MDIO_MODE_MDIO			 (1L<<9)
2355 #define BNX_EMAC_MDIO_MODE_MDIO_OE			 (1L<<10)
2356 #define BNX_EMAC_MDIO_MODE_MDC				 (1L<<11)
2357 #define BNX_EMAC_MDIO_MODE_MDINT			 (1L<<12)
2361 #define BNX_EMAC_MDIO_AUTO_STATUS_AUTO_ERR		 (1L<<0)
2364 #define BNX_EMAC_TX_MODE_RESET				 (1L<<0)
2365 #define BNX_EMAC_TX_MODE_EXT_PAUSE_EN			 (1L<<3)
2366 #define BNX_EMAC_TX_MODE_FLOW_EN			 (1L<<4)
2367 #define BNX_EMAC_TX_MODE_BIG_BACKOFF			 (1L<<5)
2368 #define BNX_EMAC_TX_MODE_LONG_PAUSE			 (1L<<6)
2369 #define BNX_EMAC_TX_MODE_LINK_AWARE			 (1L<<7)
2372 #define BNX_EMAC_TX_STATUS_XOFFED			 (1L<<0)
2373 #define BNX_EMAC_TX_STATUS_XOFF_SENT			 (1L<<1)
2374 #define BNX_EMAC_TX_STATUS_XON_SENT			 (1L<<2)
2375 #define BNX_EMAC_TX_STATUS_LINK_UP			 (1L<<3)
2376 #define BNX_EMAC_TX_STATUS_UNDERRUN			 (1L<<4)
2384 #define BNX_EMAC_RX_MODE_RESET				 (1L<<0)
2385 #define BNX_EMAC_RX_MODE_FLOW_EN			 (1L<<2)
2386 #define BNX_EMAC_RX_MODE_KEEP_MAC_CONTROL		 (1L<<3)
2387 #define BNX_EMAC_RX_MODE_KEEP_PAUSE			 (1L<<4)
2388 #define BNX_EMAC_RX_MODE_ACCEPT_OVERSIZE		 (1L<<5)
2389 #define BNX_EMAC_RX_MODE_ACCEPT_RUNTS			 (1L<<6)
2390 #define BNX_EMAC_RX_MODE_LLC_CHK			 (1L<<7)
2391 #define BNX_EMAC_RX_MODE_PROMISCUOUS			 (1L<<8)
2392 #define BNX_EMAC_RX_MODE_NO_CRC_CHK			 (1L<<9)
2393 #define BNX_EMAC_RX_MODE_KEEP_VLAN_TAG			 (1L<<10)
2394 #define BNX_EMAC_RX_MODE_FILT_BROADCAST		 (1L<<11)
2395 #define BNX_EMAC_RX_MODE_SORT_MODE			 (1L<<12)
2398 #define BNX_EMAC_RX_STATUS_FFED			 (1L<<0)
2399 #define BNX_EMAC_RX_STATUS_FF_RECEIVED			 (1L<<1)
2400 #define BNX_EMAC_RX_STATUS_N_RECEIVED			 (1L<<2)
2435 #define BNX_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT	 (1L<<0)
2436 #define BNX_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE		 (1L<<1)
2437 #define BNX_EMAC_RXMAC_DEBUG1_BAD_CRC			 (1L<<2)
2438 #define BNX_EMAC_RXMAC_DEBUG1_RX_ERROR			 (1L<<3)
2439 #define BNX_EMAC_RXMAC_DEBUG1_ALIGN_ERROR		 (1L<<4)
2440 #define BNX_EMAC_RXMAC_DEBUG1_LAST_DATA		 (1L<<5)
2441 #define BNX_EMAC_RXMAC_DEBUG1_ODD_BYTE_START		 (1L<<6)
2466 #define BNX_EMAC_RXMAC_DEBUG2_FALSEC			 (1L<<15)
2467 #define BNX_EMAC_RXMAC_DEBUG2_TAGGED			 (1L<<16)
2468 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE		 (1L<<18)
2469 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE		 (0L<<18)
2470 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED	 (1L<<18)
2521 #define BNX_EMAC_RXMAC_DEBUG4_DROP_PKT			 (1L<<22)
2522 #define BNX_EMAC_RXMAC_DEBUG4_SLOT_FILLED		 (1L<<23)
2523 #define BNX_EMAC_RXMAC_DEBUG4_FALSE_CARRIER		 (1L<<24)
2524 #define BNX_EMAC_RXMAC_DEBUG4_LAST_DATA		 (1L<<25)
2525 #define BNX_EMAC_RXMAC_DEBUG4_sfd_FOUND		 (1L<<26)
2526 #define BNX_EMAC_RXMAC_DEBUG4_ADVANCE			 (1L<<27)
2527 #define BNX_EMAC_RXMAC_DEBUG4_START			 (1L<<28)
2531 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE		 (0L<<0)
2532 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF	 (1L<<0)
2533 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT	 (2L<<0)
2534 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC	 (3L<<0)
2535 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE	 (4L<<0)
2536 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL	 (5L<<0)
2537 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT	 (6L<<0)
2546 #define BNX_EMAC_RXMAC_DEBUG5_EOF_DETECTED		 (1L<<7)
2548 #define BNX_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL	 (1L<<11)
2549 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_CCODE		 (1L<<12)
2550 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_DATA		 (1L<<13)
2551 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_STAT		 (1L<<14)
2552 #define BNX_EMAC_RXMAC_DEBUG5_CLR_STAT			 (1L<<15)
2554 #define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT		 (1L<<19)
2614 #define BNX_EMAC_TXMAC_DEBUG1_CRS_ENABLE		 (1L<<4)
2615 #define BNX_EMAC_TXMAC_DEBUG1_BAD_CRC			 (1L<<5)
2617 #define BNX_EMAC_TXMAC_DEBUG1_SEND_PAUSE		 (1L<<10)
2618 #define BNX_EMAC_TXMAC_DEBUG1_LATE_COLLISION		 (1L<<11)
2619 #define BNX_EMAC_TXMAC_DEBUG1_MAX_DEFER		 (1L<<12)
2620 #define BNX_EMAC_TXMAC_DEBUG1_DEFERRED			 (1L<<13)
2621 #define BNX_EMAC_TXMAC_DEBUG1_ONE_BYTE			 (1L<<14)
2629 #define BNX_EMAC_TXMAC_DEBUG2_COL_BIT			 (1L<<31)
2656 #define BNX_EMAC_TXMAC_DEBUG3_CRS_DONE			 (1L<<7)
2657 #define BNX_EMAC_TXMAC_DEBUG3_XOFF			 (1L<<8)
2677 #define BNX_EMAC_TXMAC_DEBUG4_STATS0_VALID		 (1L<<20)
2678 #define BNX_EMAC_TXMAC_DEBUG4_APPEND_CRC		 (1L<<21)
2679 #define BNX_EMAC_TXMAC_DEBUG4_SLOT_FILLED		 (1L<<22)
2680 #define BNX_EMAC_TXMAC_DEBUG4_MAX_DEFER		 (1L<<23)
2681 #define BNX_EMAC_TXMAC_DEBUG4_SEND_EXTEND		 (1L<<24)
2682 #define BNX_EMAC_TXMAC_DEBUG4_SEND_PADDING		 (1L<<25)
2683 #define BNX_EMAC_TXMAC_DEBUG4_EOF_LOC			 (1L<<26)
2684 #define BNX_EMAC_TXMAC_DEBUG4_COLLIDING		 (1L<<27)
2685 #define BNX_EMAC_TXMAC_DEBUG4_COL_IN			 (1L<<28)
2686 #define BNX_EMAC_TXMAC_DEBUG4_BURSTING			 (1L<<29)
2687 #define BNX_EMAC_TXMAC_DEBUG4_ADVANCE			 (1L<<30)
2688 #define BNX_EMAC_TXMAC_DEBUG4_GO			 (1L<<31)
2720 #define BNX_RPM_COMMAND_ENABLED			 (1L<<0)
2721 #define BNX_RPM_COMMAND_OVERRUN_ABORT			 (1L<<4)
2724 #define BNX_RPM_STATUS_MBUF_WAIT			 (1L<<0)
2725 #define BNX_RPM_STATUS_FREE_WAIT			 (1L<<1)
2728 #define BNX_RPM_CONFIG_NO_PSD_HDR_CKSUM		 (1L<<0)
2729 #define BNX_RPM_CONFIG_ACPI_ENA			 (1L<<1)
2730 #define BNX_RPM_CONFIG_ACPI_KEEP			 (1L<<2)
2731 #define BNX_RPM_CONFIG_MP_KEEP				 (1L<<3)
2733 #define BNX_RPM_CONFIG_IGNORE_VLAN			 (1L<<31)
2749 #define BNX_RPM_SORT_USER0_BC_EN			 (1L<<16)
2750 #define BNX_RPM_SORT_USER0_MC_EN			 (1L<<17)
2751 #define BNX_RPM_SORT_USER0_MC_HSH_EN			 (1L<<18)
2752 #define BNX_RPM_SORT_USER0_PROM_EN			 (1L<<19)
2754 #define BNX_RPM_SORT_USER0_PROM_VLAN			 (1L<<24)
2755 #define BNX_RPM_SORT_USER0_ENA				 (1L<<31)
2759 #define BNX_RPM_SORT_USER1_BC_EN			 (1L<<16)
2760 #define BNX_RPM_SORT_USER1_MC_EN			 (1L<<17)
2761 #define BNX_RPM_SORT_USER1_MC_HSH_EN			 (1L<<18)
2762 #define BNX_RPM_SORT_USER1_PROM_EN			 (1L<<19)
2764 #define BNX_RPM_SORT_USER1_PROM_VLAN			 (1L<<24)
2765 #define BNX_RPM_SORT_USER1_ENA				 (1L<<31)
2769 #define BNX_RPM_SORT_USER2_BC_EN			 (1L<<16)
2770 #define BNX_RPM_SORT_USER2_MC_EN			 (1L<<17)
2771 #define BNX_RPM_SORT_USER2_MC_HSH_EN			 (1L<<18)
2772 #define BNX_RPM_SORT_USER2_PROM_EN			 (1L<<19)
2774 #define BNX_RPM_SORT_USER2_PROM_VLAN			 (1L<<24)
2775 #define BNX_RPM_SORT_USER2_ENA				 (1L<<31)
2779 #define BNX_RPM_SORT_USER3_BC_EN			 (1L<<16)
2780 #define BNX_RPM_SORT_USER3_MC_EN			 (1L<<17)
2781 #define BNX_RPM_SORT_USER3_MC_HSH_EN			 (1L<<18)
2782 #define BNX_RPM_SORT_USER3_PROM_EN			 (1L<<19)
2784 #define BNX_RPM_SORT_USER3_PROM_VLAN			 (1L<<24)
2785 #define BNX_RPM_SORT_USER3_ENA				 (1L<<31)
2800 #define BNX_RPM_RC_CNTL_0_PRIORITY			 (1L<<11)
2801 #define BNX_RPM_RC_CNTL_0_P4				 (1L<<12)
2803 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_START		 (0L<<13)
2804 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_IP			 (1L<<13)
2805 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_TCP			 (2L<<13)
2806 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_UDP			 (3L<<13)
2807 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_DATA		 (4L<<13)
2809 #define BNX_RPM_RC_CNTL_0_COMP_EQUAL			 (0L<<16)
2810 #define BNX_RPM_RC_CNTL_0_COMP_NEQUAL			 (1L<<16)
2811 #define BNX_RPM_RC_CNTL_0_COMP_GREATER			 (2L<<16)
2812 #define BNX_RPM_RC_CNTL_0_COMP_LESS			 (3L<<16)
2813 #define BNX_RPM_RC_CNTL_0_SBIT				 (1L<<19)
2815 #define BNX_RPM_RC_CNTL_0_MAP				 (1L<<24)
2816 #define BNX_RPM_RC_CNTL_0_DISCARD			 (1L<<25)
2817 #define BNX_RPM_RC_CNTL_0_MASK				 (1L<<26)
2818 #define BNX_RPM_RC_CNTL_0_P1				 (1L<<27)
2819 #define BNX_RPM_RC_CNTL_0_P2				 (1L<<28)
2820 #define BNX_RPM_RC_CNTL_0_P3				 (1L<<29)
2821 #define BNX_RPM_RC_CNTL_0_NBIT				 (1L<<30)
2908 #define BNX_RPM_DEBUG0_T_DATA_OFST_VLD			 (1L<<16)
2909 #define BNX_RPM_DEBUG0_T_UDP_OFST_VLD			 (1L<<17)
2910 #define BNX_RPM_DEBUG0_T_TCP_OFST_VLD			 (1L<<18)
2911 #define BNX_RPM_DEBUG0_T_IP_OFST_VLD			 (1L<<19)
2912 #define BNX_RPM_DEBUG0_IP_MORE_FRGMT			 (1L<<20)
2913 #define BNX_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR		 (1L<<21)
2914 #define BNX_RPM_DEBUG0_LLC_SNAP			 (1L<<22)
2915 #define BNX_RPM_DEBUG0_FM_STARTED			 (1L<<23)
2916 #define BNX_RPM_DEBUG0_DONE				 (1L<<24)
2917 #define BNX_RPM_DEBUG0_WAIT_4_DONE			 (1L<<25)
2918 #define BNX_RPM_DEBUG0_USE_TPBUF_CKSUM			 (1L<<26)
2919 #define BNX_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM		 (1L<<27)
2920 #define BNX_RPM_DEBUG0_IGNORE_VLAN			 (1L<<28)
2921 #define BNX_RPM_DEBUG0_RP_ENA_ACTIVE			 (1L<<31)
2925 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IDLE			 (0L<<0)
2926 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL		 (1L<<0)
2927 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC	 (2L<<0)
2928 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP		 (4L<<0)
2929 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP		 (8L<<0)
2930 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IP_START		 (16L<<0)
2931 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IP			 (32L<<0)
2932 #define BNX_RPM_DEBUG1_FSM_CUR_ST_TCP			 (64L<<0)
2933 #define BNX_RPM_DEBUG1_FSM_CUR_ST_UDP			 (128L<<0)
2934 #define BNX_RPM_DEBUG1_FSM_CUR_ST_AH			 (256L<<0)
2935 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP			 (512L<<0)
2936 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD		 (1024L<<0)
2937 #define BNX_RPM_DEBUG1_FSM_CUR_ST_DATA			 (2048L<<0)
2942 #define BNX_RPM_DEBUG1_UNKNOWN_ETYPE_D			 (1L<<28)
2943 #define BNX_RPM_DEBUG1_VLAN_REMOVED_D2			 (1L<<29)
2944 #define BNX_RPM_DEBUG1_VLAN_REMOVED_D1			 (1L<<30)
2945 #define BNX_RPM_DEBUG1_EOF_0XTRA_WD			 (1L<<31)
2950 #define BNX_RPM_DEBUG2_THIS_CMD_M4			 (1L<<24)
2951 #define BNX_RPM_DEBUG2_THIS_CMD_M3			 (1L<<25)
2952 #define BNX_RPM_DEBUG2_THIS_CMD_M2			 (1L<<26)
2953 #define BNX_RPM_DEBUG2_THIS_CMD_M1			 (1L<<27)
2954 #define BNX_RPM_DEBUG2_IPIPE_EMPTY			 (1L<<28)
2955 #define BNX_RPM_DEBUG2_FM_DISCARD			 (1L<<29)
2956 #define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D2		 (1L<<30)
2957 #define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D1		 (1L<<31)
2961 #define BNX_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT		 (1L<<9)
2962 #define BNX_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT		 (1L<<10)
2963 #define BNX_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT		 (1L<<11)
2964 #define BNX_RPM_DEBUG3_RDE_RBUF_FREE_REQ		 (1L<<12)
2965 #define BNX_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ		 (1L<<13)
2966 #define BNX_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL		 (1L<<14)
2967 #define BNX_RPM_DEBUG3_RBUF_RDE_SOF_DROP		 (1L<<15)
2969 #define BNX_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL		 (1L<<21)
2970 #define BNX_RPM_DEBUG3_DROP_NXT_VLD			 (1L<<22)
2971 #define BNX_RPM_DEBUG3_DROP_NXT			 (1L<<23)
2985 #define BNX_RPM_DEBUG3_MBFREE_FSM			 (1L<<29)
2986 #define BNX_RPM_DEBUG3_MBFREE_FSM_IDLE			 (0L<<29)
2987 #define BNX_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK		 (1L<<29)
2988 #define BNX_RPM_DEBUG3_MBALLOC_FSM			 (1L<<30)
2991 #define BNX_RPM_DEBUG3_CCODE_EOF_ERROR			 (1L<<31)
2997 #define BNX_RPM_DEBUG4_DFIFO_EMPTY			 (1L<<31)
3004 #define BNX_RPM_DEBUG5_RDROP_ACPI_EMPTY		 (1L<<20)
3005 #define BNX_RPM_DEBUG5_RDROP_MC_EMPTY			 (1L<<21)
3006 #define BNX_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR	 (1L<<22)
3007 #define BNX_RPM_DEBUG5_HOLDREG_WOL_DROP_INT		 (1L<<23)
3008 #define BNX_RPM_DEBUG5_HOLDREG_DISCARD			 (1L<<24)
3009 #define BNX_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL		 (1L<<25)
3010 #define BNX_RPM_DEBUG5_HOLDREG_MC_EMPTY		 (1L<<26)
3011 #define BNX_RPM_DEBUG5_HOLDREG_RC_EMPTY		 (1L<<27)
3012 #define BNX_RPM_DEBUG5_HOLDREG_FC_EMPTY		 (1L<<28)
3013 #define BNX_RPM_DEBUG5_HOLDREG_ACPI_EMPTY		 (1L<<29)
3014 #define BNX_RPM_DEBUG5_HOLDREG_FULL_T			 (1L<<30)
3015 #define BNX_RPM_DEBUG5_HOLDREG_RD			 (1L<<31)
3026 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_IDLE		 (0L<<0)
3027 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR		 (1L<<0)
3028 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR		 (2L<<0)
3029 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR		 (3L<<0)
3030 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF	 (4L<<0)
3031 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA		 (5L<<0)
3032 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR		 (6L<<0)
3033 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR		 (7L<<0)
3034 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR		 (8L<<0)
3035 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR		 (9L<<0)
3036 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF		 (10L<<0)
3037 #define BNX_RPM_DEBUG8_COMPARE_AT_W0			 (1L<<4)
3038 #define BNX_RPM_DEBUG8_COMPARE_AT_W3_DATA		 (1L<<5)
3039 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_WAIT		 (1L<<6)
3040 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W3		 (1L<<7)
3041 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W2		 (1L<<8)
3042 #define BNX_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES		 (1L<<9)
3043 #define BNX_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES		 (1L<<10)
3044 #define BNX_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES		 (1L<<11)
3045 #define BNX_RPM_DEBUG8_EOF_DET				 (1L<<12)
3046 #define BNX_RPM_DEBUG8_SOF_DET				 (1L<<13)
3047 #define BNX_RPM_DEBUG8_WAIT_4_SOF			 (1L<<14)
3048 #define BNX_RPM_DEBUG8_ALL_DONE			 (1L<<15)
3054 #define BNX_RPM_DEBUG9_RDE_ACPI_RDY			 (1L<<3)
3056 #define BNX_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED	 (1L<<28)
3057 #define BNX_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED		 (1L<<29)
3058 #define BNX_RPM_DEBUG9_ACPI_MATCH_INT			 (1L<<30)
3059 #define BNX_RPM_DEBUG9_ACPI_ENABLE_SYN			 (1L<<31)
3084 #define BNX_RBUF_COMMAND_ENABLED			 (1L<<0)
3085 #define BNX_RBUF_COMMAND_FREE_INIT			 (1L<<1)
3086 #define BNX_RBUF_COMMAND_RAM_INIT			 (1L<<2)
3087 #define BNX_RBUF_COMMAND_OVER_FREE			 (1L<<4)
3088 #define BNX_RBUF_COMMAND_ALLOC_REQ			 (1L<<5)
3132 #define BNX_RV2P_COMMAND_ENABLED			 (1L<<0)
3133 #define BNX_RV2P_COMMAND_PROC1_INTRPT			 (1L<<1)
3134 #define BNX_RV2P_COMMAND_PROC2_INTRPT			 (1L<<2)
3135 #define BNX_RV2P_COMMAND_ABORT0			 (1L<<4)
3136 #define BNX_RV2P_COMMAND_ABORT1			 (1L<<5)
3137 #define BNX_RV2P_COMMAND_ABORT2			 (1L<<6)
3138 #define BNX_RV2P_COMMAND_ABORT3			 (1L<<7)
3139 #define BNX_RV2P_COMMAND_ABORT4			 (1L<<8)
3140 #define BNX_RV2P_COMMAND_ABORT5			 (1L<<9)
3141 #define BNX_RV2P_COMMAND_PROC1_RESET			 (1L<<16)
3142 #define BNX_RV2P_COMMAND_PROC2_RESET			 (1L<<17)
3143 #define BNX_RV2P_COMMAND_CTXIF_RESET			 (1L<<18)
3146 #define BNX_RV2P_STATUS_ALWAYS_0			 (1L<<0)
3147 #define BNX_RV2P_STATUS_RV2P_GEN_STAT0_CNT		 (1L<<8)
3148 #define BNX_RV2P_STATUS_RV2P_GEN_STAT1_CNT		 (1L<<9)
3149 #define BNX_RV2P_STATUS_RV2P_GEN_STAT2_CNT		 (1L<<10)
3150 #define BNX_RV2P_STATUS_RV2P_GEN_STAT3_CNT		 (1L<<11)
3151 #define BNX_RV2P_STATUS_RV2P_GEN_STAT4_CNT		 (1L<<12)
3152 #define BNX_RV2P_STATUS_RV2P_GEN_STAT5_CNT		 (1L<<13)
3155 #define BNX_RV2P_CONFIG_STALL_PROC1			 (1L<<0)
3156 #define BNX_RV2P_CONFIG_STALL_PROC2			 (1L<<1)
3157 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT0		 (1L<<8)
3158 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT1		 (1L<<9)
3159 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT2		 (1L<<10)
3160 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT3		 (1L<<11)
3161 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT4		 (1L<<12)
3162 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT5		 (1L<<13)
3163 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT0		 (1L<<16)
3164 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT1		 (1L<<17)
3165 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT2		 (1L<<18)
3166 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT3		 (1L<<19)
3167 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT4		 (1L<<20)
3168 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT5		 (1L<<21)
3170 #define BNX_RV2P_CONFIG_PAGE_SIZE_256			 (0L<<24)
3171 #define BNX_RV2P_CONFIG_PAGE_SIZE_512			 (1L<<24)
3172 #define BNX_RV2P_CONFIG_PAGE_SIZE_1K			 (2L<<24)
3173 #define BNX_RV2P_CONFIG_PAGE_SIZE_2K			 (3L<<24)
3174 #define BNX_RV2P_CONFIG_PAGE_SIZE_4K			 (4L<<24)
3175 #define BNX_RV2P_CONFIG_PAGE_SIZE_8K			 (5L<<24)
3176 #define BNX_RV2P_CONFIG_PAGE_SIZE_16K			 (6L<<24)
3177 #define BNX_RV2P_CONFIG_PAGE_SIZE_32K			 (7L<<24)
3178 #define BNX_RV2P_CONFIG_PAGE_SIZE_64K			 (8L<<24)
3179 #define BNX_RV2P_CONFIG_PAGE_SIZE_128K			 (9L<<24)
3180 #define BNX_RV2P_CONFIG_PAGE_SIZE_256K			 (10L<<24)
3181 #define BNX_RV2P_CONFIG_PAGE_SIZE_512K			 (11L<<24)
3182 #define BNX_RV2P_CONFIG_PAGE_SIZE_1M			 (12L<<24)
3202 #define BNX_RV2P_PROC1_ADDR_CMD_RDWR			 (1L<<31)
3206 #define BNX_RV2P_PROC2_ADDR_CMD_RDWR			 (1L<<31)
3213 #define BNX_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
3216 #define BNX_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
3222 #define BNX_RV2P_PFTQ_CMD_WR_TOP			 (1L<<10)
3223 #define BNX_RV2P_PFTQ_CMD_WR_TOP_0			 (0L<<10)
3224 #define BNX_RV2P_PFTQ_CMD_WR_TOP_1			 (1L<<10)
3225 #define BNX_RV2P_PFTQ_CMD_SFT_RESET			 (1L<<25)
3226 #define BNX_RV2P_PFTQ_CMD_RD_DATA			 (1L<<26)
3227 #define BNX_RV2P_PFTQ_CMD_ADD_INTERVEN			 (1L<<27)
3228 #define BNX_RV2P_PFTQ_CMD_ADD_DATA			 (1L<<28)
3229 #define BNX_RV2P_PFTQ_CMD_INTERVENE_CLR		 (1L<<29)
3230 #define BNX_RV2P_PFTQ_CMD_POP				 (1L<<30)
3231 #define BNX_RV2P_PFTQ_CMD_BUSY				 (1L<<31)
3234 #define BNX_RV2P_PFTQ_CTL_INTERVENE			 (1L<<0)
3235 #define BNX_RV2P_PFTQ_CTL_OVERFLOW			 (1L<<1)
3236 #define BNX_RV2P_PFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3243 #define BNX_RV2P_TFTQ_CMD_WR_TOP			 (1L<<10)
3244 #define BNX_RV2P_TFTQ_CMD_WR_TOP_0			 (0L<<10)
3245 #define BNX_RV2P_TFTQ_CMD_WR_TOP_1			 (1L<<10)
3246 #define BNX_RV2P_TFTQ_CMD_SFT_RESET			 (1L<<25)
3247 #define BNX_RV2P_TFTQ_CMD_RD_DATA			 (1L<<26)
3248 #define BNX_RV2P_TFTQ_CMD_ADD_INTERVEN			 (1L<<27)
3249 #define BNX_RV2P_TFTQ_CMD_ADD_DATA			 (1L<<28)
3250 #define BNX_RV2P_TFTQ_CMD_INTERVENE_CLR		 (1L<<29)
3251 #define BNX_RV2P_TFTQ_CMD_POP				 (1L<<30)
3252 #define BNX_RV2P_TFTQ_CMD_BUSY				 (1L<<31)
3255 #define BNX_RV2P_TFTQ_CTL_INTERVENE			 (1L<<0)
3256 #define BNX_RV2P_TFTQ_CTL_OVERFLOW			 (1L<<1)
3257 #define BNX_RV2P_TFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3264 #define BNX_RV2P_MFTQ_CMD_WR_TOP			 (1L<<10)
3265 #define BNX_RV2P_MFTQ_CMD_WR_TOP_0			 (0L<<10)
3266 #define BNX_RV2P_MFTQ_CMD_WR_TOP_1			 (1L<<10)
3267 #define BNX_RV2P_MFTQ_CMD_SFT_RESET			 (1L<<25)
3268 #define BNX_RV2P_MFTQ_CMD_RD_DATA			 (1L<<26)
3269 #define BNX_RV2P_MFTQ_CMD_ADD_INTERVEN			 (1L<<27)
3270 #define BNX_RV2P_MFTQ_CMD_ADD_DATA			 (1L<<28)
3271 #define BNX_RV2P_MFTQ_CMD_INTERVENE_CLR		 (1L<<29)
3272 #define BNX_RV2P_MFTQ_CMD_POP				 (1L<<30)
3273 #define BNX_RV2P_MFTQ_CMD_BUSY				 (1L<<31)
3276 #define BNX_RV2P_MFTQ_CTL_INTERVENE			 (1L<<0)
3277 #define BNX_RV2P_MFTQ_CTL_OVERFLOW			 (1L<<1)
3278 #define BNX_RV2P_MFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3289 #define BNX_MQ_COMMAND_ENABLED				 (1L<<0)
3290 #define BNX_MQ_COMMAND_OVERFLOW			 (1L<<4)
3291 #define BNX_MQ_COMMAND_WR_ERROR			 (1L<<5)
3292 #define BNX_MQ_COMMAND_RD_ERROR			 (1L<<6)
3295 #define BNX_MQ_STATUS_CTX_ACCESS_STAT			 (1L<<16)
3296 #define BNX_MQ_STATUS_CTX_ACCESS64_STAT		 (1L<<17)
3297 #define BNX_MQ_STATUS_PCI_STALL_STAT			 (1L<<18)
3300 #define BNX_MQ_CONFIG_TX_HIGH_PRI			 (1L<<0)
3301 #define BNX_MQ_CONFIG_HALT_DIS				 (1L<<1)
3302 #define BNX_MQ_CONFIG_BIN_MQ_MODE			 (1L<<2)
3303 #define BNX_MQ_CONFIG_DIS_IDB_DROP			 (1L<<3)
3305 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256		 (0L<<4)
3306 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_512		 (1L<<4)
3307 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K		 (2L<<4)
3308 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K		 (3L<<4)
3309 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K		 (4L<<4)
3317 #define BNX_MQ_ENQUEUE1_KNL_MODE			 (1L<<28)
3387 #define BNX_TBDR_COMMAND_ENABLE			 (1L<<0)
3388 #define BNX_TBDR_COMMAND_SOFT_RST			 (1L<<1)
3389 #define BNX_TBDR_COMMAND_MSTR_ABORT			 (1L<<4)
3392 #define BNX_TBDR_STATUS_DMA_WAIT			 (1L<<0)
3393 #define BNX_TBDR_STATUS_FTQ_WAIT			 (1L<<1)
3394 #define BNX_TBDR_STATUS_FIFO_OVERFLOW			 (1L<<2)
3395 #define BNX_TBDR_STATUS_FIFO_UNDERFLOW			 (1L<<3)
3396 #define BNX_TBDR_STATUS_SEARCHMISS_ERROR		 (1L<<4)
3397 #define BNX_TBDR_STATUS_FTQ_ENTRY_CNT			 (1L<<5)
3398 #define BNX_TBDR_STATUS_BURST_CNT			 (1L<<6)
3402 #define BNX_TBDR_CONFIG_SWAP_MODE			 (1L<<8)
3403 #define BNX_TBDR_CONFIG_PRIORITY			 (1L<<9)
3404 #define BNX_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS		 (1L<<10)
3406 #define BNX_TBDR_CONFIG_PAGE_SIZE_256			 (0L<<24)
3407 #define BNX_TBDR_CONFIG_PAGE_SIZE_512			 (1L<<24)
3408 #define BNX_TBDR_CONFIG_PAGE_SIZE_1K			 (2L<<24)
3409 #define BNX_TBDR_CONFIG_PAGE_SIZE_2K			 (3L<<24)
3410 #define BNX_TBDR_CONFIG_PAGE_SIZE_4K			 (4L<<24)
3411 #define BNX_TBDR_CONFIG_PAGE_SIZE_8K			 (5L<<24)
3412 #define BNX_TBDR_CONFIG_PAGE_SIZE_16K			 (6L<<24)
3413 #define BNX_TBDR_CONFIG_PAGE_SIZE_32K			 (7L<<24)
3414 #define BNX_TBDR_CONFIG_PAGE_SIZE_64K			 (8L<<24)
3415 #define BNX_TBDR_CONFIG_PAGE_SIZE_128K			 (9L<<24)
3416 #define BNX_TBDR_CONFIG_PAGE_SIZE_256K			 (10L<<24)
3417 #define BNX_TBDR_CONFIG_PAGE_SIZE_512K			 (11L<<24)
3418 #define BNX_TBDR_CONFIG_PAGE_SIZE_1M			 (12L<<24)
3422 #define BNX_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
3425 #define BNX_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
3431 #define BNX_TBDR_FTQ_CMD_WR_TOP			 (1L<<10)
3432 #define BNX_TBDR_FTQ_CMD_WR_TOP_0			 (0L<<10)
3433 #define BNX_TBDR_FTQ_CMD_WR_TOP_1			 (1L<<10)
3434 #define BNX_TBDR_FTQ_CMD_SFT_RESET			 (1L<<25)
3435 #define BNX_TBDR_FTQ_CMD_RD_DATA			 (1L<<26)
3436 #define BNX_TBDR_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
3437 #define BNX_TBDR_FTQ_CMD_ADD_DATA			 (1L<<28)
3438 #define BNX_TBDR_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
3439 #define BNX_TBDR_FTQ_CMD_POP				 (1L<<30)
3440 #define BNX_TBDR_FTQ_CMD_BUSY				 (1L<<31)
3443 #define BNX_TBDR_FTQ_CTL_INTERVENE			 (1L<<0)
3444 #define BNX_TBDR_FTQ_CTL_OVERFLOW			 (1L<<1)
3445 #define BNX_TBDR_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3456 #define BNX_TDMA_COMMAND_ENABLED			 (1L<<0)
3457 #define BNX_TDMA_COMMAND_MASTER_ABORT			 (1L<<4)
3458 #define BNX_TDMA_COMMAND_BAD_L2_LENGTH_ABORT		 (1L<<7)
3461 #define BNX_TDMA_STATUS_DMA_WAIT			 (1L<<0)
3462 #define BNX_TDMA_STATUS_PAYLOAD_WAIT			 (1L<<1)
3463 #define BNX_TDMA_STATUS_PATCH_FTQ_WAIT			 (1L<<2)
3464 #define BNX_TDMA_STATUS_LOCK_WAIT			 (1L<<3)
3465 #define BNX_TDMA_STATUS_FTQ_ENTRY_CNT			 (1L<<16)
3466 #define BNX_TDMA_STATUS_BURST_CNT			 (1L<<17)
3469 #define BNX_TDMA_CONFIG_ONE_DMA			 (1L<<0)
3470 #define BNX_TDMA_CONFIG_ONE_RECORD			 (1L<<1)
3472 #define BNX_TDMA_CONFIG_LIMIT_SZ_64			 (0L<<4)
3477 #define BNX_TDMA_CONFIG_LINE_SZ_64			 (0L<<8)
3478 #define BNX_TDMA_CONFIG_LINE_SZ_128			 (4L<<8)
3479 #define BNX_TDMA_CONFIG_LINE_SZ_256			 (6L<<8)
3480 #define BNX_TDMA_CONFIG_LINE_SZ_512			 (8L<<8)
3481 #define BNX_TDMA_CONFIG_ALIGN_ENA			 (1L<<15)
3482 #define BNX_TDMA_CONFIG_CHK_L2_BD			 (1L<<16)
3491 #define BNX_TDMA_DMAD_FSM_BD_INVLD			 (1L<<0)
3494 #define BNX_TDMA_DMAD_FSM_ARB_CTX			 (1L<<12)
3495 #define BNX_TDMA_DMAD_FSM_DR_INTF			 (1L<<16)
3522 #define BNX_TDMA_FTQ_CMD_WR_TOP			 (1L<<10)
3523 #define BNX_TDMA_FTQ_CMD_WR_TOP_0			 (0L<<10)
3524 #define BNX_TDMA_FTQ_CMD_WR_TOP_1			 (1L<<10)
3525 #define BNX_TDMA_FTQ_CMD_SFT_RESET			 (1L<<25)
3526 #define BNX_TDMA_FTQ_CMD_RD_DATA			 (1L<<26)
3527 #define BNX_TDMA_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
3528 #define BNX_TDMA_FTQ_CMD_ADD_DATA			 (1L<<28)
3529 #define BNX_TDMA_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
3530 #define BNX_TDMA_FTQ_CMD_POP				 (1L<<30)
3531 #define BNX_TDMA_FTQ_CMD_BUSY				 (1L<<31)
3534 #define BNX_TDMA_FTQ_CTL_INTERVENE			 (1L<<0)
3535 #define BNX_TDMA_FTQ_CTL_OVERFLOW			 (1L<<1)
3536 #define BNX_TDMA_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3547 #define BNX_HC_COMMAND_ENABLE				 (1L<<0)
3548 #define BNX_HC_COMMAND_SKIP_ABORT			 (1L<<4)
3549 #define BNX_HC_COMMAND_COAL_NOW			 (1L<<16)
3550 #define BNX_HC_COMMAND_COAL_NOW_WO_INT			 (1L<<17)
3551 #define BNX_HC_COMMAND_STATS_NOW			 (1L<<18)
3553 #define BNX_HC_COMMAND_FORCE_INT_NULL			 (0L<<19)
3554 #define BNX_HC_COMMAND_FORCE_INT_HIGH			 (1L<<19)
3555 #define BNX_HC_COMMAND_FORCE_INT_LOW			 (2L<<19)
3556 #define BNX_HC_COMMAND_FORCE_INT_FREE			 (3L<<19)
3557 #define BNX_HC_COMMAND_CLR_STAT_NOW			 (1L<<21)
3560 #define BNX_HC_STATUS_MASTER_ABORT			 (1L<<0)
3561 #define BNX_HC_STATUS_PARITY_ERROR_STATE		 (1L<<1)
3562 #define BNX_HC_STATUS_PCI_CLK_CNT_STAT			 (1L<<16)
3563 #define BNX_HC_STATUS_CORE_CLK_CNT_STAT		 (1L<<17)
3564 #define BNX_HC_STATUS_NUM_STATUS_BLOCKS_STAT		 (1L<<18)
3565 #define BNX_HC_STATUS_NUM_INT_GEN_STAT			 (1L<<19)
3566 #define BNX_HC_STATUS_NUM_INT_MBOX_WR_STAT		 (1L<<20)
3567 #define BNX_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT	 (1L<<23)
3568 #define BNX_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT	 (1L<<24)
3569 #define BNX_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT	 (1L<<25)
3572 #define BNX_HC_CONFIG_COLLECT_STATS			 (1L<<0)
3573 #define BNX_HC_CONFIG_RX_TMR_MODE			 (1L<<1)
3574 #define BNX_HC_CONFIG_TX_TMR_MODE			 (1L<<2)
3575 #define BNX_HC_CONFIG_COM_TMR_MODE			 (1L<<3)
3576 #define BNX_HC_CONFIG_CMD_TMR_MODE			 (1L<<4)
3577 #define BNX_HC_CONFIG_STATISTIC_PRIORITY		 (1L<<5)
3578 #define BNX_HC_CONFIG_STATUS_PRIORITY			 (1L<<6)
3626 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0	 (0L<<0)
3627 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1	 (1L<<0)
3628 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2	 (2L<<0)
3629 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3	 (3L<<0)
3630 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4	 (4L<<0)
3631 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5	 (5L<<0)
3632 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6	 (6L<<0)
3633 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7	 (7L<<0)
3634 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8	 (8L<<0)
3635 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9	 (9L<<0)
3636 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10	 (10L<<0)
3637 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11	 (11L<<0)
3638 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0	 (12L<<0)
3639 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1	 (13L<<0)
3640 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2	 (14L<<0)
3641 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3	 (15L<<0)
3642 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4	 (16L<<0)
3643 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5	 (17L<<0)
3644 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6	 (18L<<0)
3645 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7	 (19L<<0)
3646 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0	 (20L<<0)
3647 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1	 (21L<<0)
3648 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2	 (22L<<0)
3649 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3	 (23L<<0)
3650 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4	 (24L<<0)
3651 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5	 (25L<<0)
3652 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6	 (26L<<0)
3653 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7	 (27L<<0)
3654 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8	 (28L<<0)
3655 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9	 (29L<<0)
3656 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10	 (30L<<0)
3657 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11	 (31L<<0)
3658 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0	 (32L<<0)
3659 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1	 (33L<<0)
3660 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2	 (34L<<0)
3661 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3	 (35L<<0)
3662 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0	 (36L<<0)
3663 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1	 (37L<<0)
3664 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2	 (38L<<0)
3665 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3	 (39L<<0)
3666 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4	 (40L<<0)
3667 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5	 (41L<<0)
3668 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6	 (42L<<0)
3669 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7	 (43L<<0)
3670 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0	 (44L<<0)
3671 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1	 (45L<<0)
3672 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2	 (46L<<0)
3673 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3	 (47L<<0)
3674 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4	 (48L<<0)
3675 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5	 (49L<<0)
3676 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6	 (50L<<0)
3677 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7	 (51L<<0)
3678 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT	 (52L<<0)
3679 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT	 (53L<<0)
3680 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS	 (54L<<0)
3681 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN	 (55L<<0)
3682 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR	 (56L<<0)
3683 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK	 (59L<<0)
3684 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK	 (60L<<0)
3685 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK	 (61L<<0)
3686 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT	 (62L<<0)
3687 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT	 (63L<<0)
3688 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT	 (64L<<0)
3689 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT	 (65L<<0)
3690 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT	 (66L<<0)
3691 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT	 (67L<<0)
3692 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT	 (68L<<0)
3693 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT	 (69L<<0)
3694 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT	 (70L<<0)
3695 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT	 (71L<<0)
3696 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT	 (72L<<0)
3697 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT	 (73L<<0)
3698 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT	 (74L<<0)
3699 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT	 (75L<<0)
3700 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT	 (76L<<0)
3701 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT	 (77L<<0)
3702 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT	 (78L<<0)
3703 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT	 (79L<<0)
3704 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT	 (80L<<0)
3705 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT	 (81L<<0)
3706 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT	 (82L<<0)
3707 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT	 (83L<<0)
3708 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT	 (84L<<0)
3709 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT	 (85L<<0)
3710 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT	 (86L<<0)
3711 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT	 (87L<<0)
3712 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT	 (88L<<0)
3713 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT	 (89L<<0)
3714 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT	 (90L<<0)
3715 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT	 (91L<<0)
3716 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT	 (92L<<0)
3717 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT	 (93L<<0)
3718 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT	 (94L<<0)
3719 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64	 (95L<<0)
3720 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64	 (96L<<0)
3721 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS	 (97L<<0)
3722 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS	 (98L<<0)
3723 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT	 (99L<<0)
3724 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT	 (100L<<0)
3725 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT	 (101L<<0)
3726 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT	 (102L<<0)
3727 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT	 (103L<<0)
3728 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT	 (104L<<0)
3729 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT	 (105L<<0)
3730 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT	 (106L<<0)
3731 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT	 (107L<<0)
3732 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT	 (108L<<0)
3733 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT	 (109L<<0)
3734 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT	 (110L<<0)
3735 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT	 (111L<<0)
3736 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT	 (112L<<0)
3737 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT	 (113L<<0)
3738 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT	 (114L<<0)
3739 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0	 (115L<<0)
3740 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1	 (116L<<0)
3741 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2	 (117L<<0)
3742 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3	 (118L<<0)
3743 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4	 (119L<<0)
3744 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5	 (120L<<0)
3745 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS	 (121L<<0)
3746 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS	 (122L<<0)
3747 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT	 (127L<<0)
3804 #define BNX_HC_VIS_STAT_BUILD_STATE_IDLE		 (0L<<0)
3805 #define BNX_HC_VIS_STAT_BUILD_STATE_START		 (1L<<0)
3806 #define BNX_HC_VIS_STAT_BUILD_STATE_REQUEST		 (2L<<0)
3807 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE64		 (3L<<0)
3808 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE32		 (4L<<0)
3809 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE	 (5L<<0)
3810 #define BNX_HC_VIS_STAT_BUILD_STATE_DMA		 (6L<<0)
3811 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL	 (7L<<0)
3812 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_LOW		 (8L<<0)
3813 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_HIGH		 (9L<<0)
3814 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_DATA		 (10L<<0)
3816 #define BNX_HC_VIS_DMA_STAT_STATE_IDLE			 (0L<<8)
3817 #define BNX_HC_VIS_DMA_STAT_STATE_STATUS_PARAM		 (1L<<8)
3818 #define BNX_HC_VIS_DMA_STAT_STATE_STATUS_DMA		 (2L<<8)
3819 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP		 (3L<<8)
3820 #define BNX_HC_VIS_DMA_STAT_STATE_COMP			 (4L<<8)
3821 #define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM	 (5L<<8)
3822 #define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA	 (6L<<8)
3823 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1		 (7L<<8)
3824 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2		 (8L<<8)
3825 #define BNX_HC_VIS_DMA_STAT_STATE_WAIT			 (9L<<8)
3826 #define BNX_HC_VIS_DMA_STAT_STATE_ABORT		 (15L<<8)
3829 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE		 (0L<<15)
3830 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT	 (1L<<15)
3831 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_START	 (2L<<15)
3834 #define BNX_HC_VIS_1_HW_INTACK_STATE			 (1L<<4)
3835 #define BNX_HC_VIS_1_HW_INTACK_STATE_IDLE		 (0L<<4)
3836 #define BNX_HC_VIS_1_HW_INTACK_STATE_COUNT		 (1L<<4)
3837 #define BNX_HC_VIS_1_SW_INTACK_STATE			 (1L<<5)
3838 #define BNX_HC_VIS_1_SW_INTACK_STATE_IDLE		 (0L<<5)
3839 #define BNX_HC_VIS_1_SW_INTACK_STATE_COUNT		 (1L<<5)
3840 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE		 (1L<<6)
3841 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE	 (0L<<6)
3842 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT	 (1L<<6)
3843 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE		 (1L<<7)
3844 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE		 (0L<<7)
3845 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT		 (1L<<7)
3847 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_IDLE		 (0L<<17)
3848 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_DMA		 (1L<<17)
3849 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE		 (2L<<17)
3850 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN		 (3L<<17)
3851 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_WAIT		 (4L<<17)
3852 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE	 (5L<<17)
3853 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN	 (6L<<17)
3854 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT		 (7L<<17)
3856 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL		 (0L<<21)
3857 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR		 (1L<<21)
3858 #define BNX_HC_VIS_1_INT_GEN_STATE			 (1L<<23)
3859 #define BNX_HC_VIS_1_INT_GEN_STATE_DLE			 (0L<<23)
3860 #define BNX_HC_VIS_1_INT_GEN_STATE_NTERRUPT		 (1L<<23)
3862 #define BNX_HC_VIS_1_INT_B				 (1L<<27)
3866 #define BNX_HC_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
3869 #define BNX_HC_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
3879 #define BNX_TXP_CPU_MODE_LOCAL_RST			 (1L<<0)
3880 #define BNX_TXP_CPU_MODE_STEP_ENA			 (1L<<1)
3881 #define BNX_TXP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
3882 #define BNX_TXP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
3883 #define BNX_TXP_CPU_MODE_MSG_BIT1			 (1L<<6)
3884 #define BNX_TXP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
3885 #define BNX_TXP_CPU_MODE_SOFT_HALT			 (1L<<10)
3886 #define BNX_TXP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
3887 #define BNX_TXP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
3888 #define BNX_TXP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
3889 #define BNX_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
3892 #define BNX_TXP_CPU_STATE_BREAKPOINT			 (1L<<0)
3893 #define BNX_TXP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
3894 #define BNX_TXP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
3895 #define BNX_TXP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
3896 #define BNX_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
3897 #define BNX_TXP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
3898 #define BNX_TXP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
3899 #define BNX_TXP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
3900 #define BNX_TXP_CPU_STATE_SOFT_HALTED			 (1L<<10)
3901 #define BNX_TXP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
3902 #define BNX_TXP_CPU_STATE_INTERRRUPT			 (1L<<12)
3903 #define BNX_TXP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
3904 #define BNX_TXP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
3905 #define BNX_TXP_CPU_STATE_BLOCKED_READ			 (1L<<31)
3908 #define BNX_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
3909 #define BNX_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
3910 #define BNX_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
3911 #define BNX_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
3912 #define BNX_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
3913 #define BNX_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
3914 #define BNX_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
3915 #define BNX_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
3916 #define BNX_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
3917 #define BNX_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
3918 #define BNX_TXP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
3927 #define BNX_TXP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
3932 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
3935 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
3939 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
3940 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)
3941 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
3948 #define BNX_TXP_FTQ_CMD_WR_TOP				 (1L<<10)
3949 #define BNX_TXP_FTQ_CMD_WR_TOP_0			 (0L<<10)
3950 #define BNX_TXP_FTQ_CMD_WR_TOP_1			 (1L<<10)
3951 #define BNX_TXP_FTQ_CMD_SFT_RESET			 (1L<<25)
3952 #define BNX_TXP_FTQ_CMD_RD_DATA			 (1L<<26)
3953 #define BNX_TXP_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
3954 #define BNX_TXP_FTQ_CMD_ADD_DATA			 (1L<<28)
3955 #define BNX_TXP_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
3956 #define BNX_TXP_FTQ_CMD_POP				 (1L<<30)
3957 #define BNX_TXP_FTQ_CMD_BUSY				 (1L<<31)
3960 #define BNX_TXP_FTQ_CTL_INTERVENE			 (1L<<0)
3961 #define BNX_TXP_FTQ_CTL_OVERFLOW			 (1L<<1)
3962 #define BNX_TXP_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3974 #define BNX_TPAT_CPU_MODE_LOCAL_RST			 (1L<<0)
3975 #define BNX_TPAT_CPU_MODE_STEP_ENA			 (1L<<1)
3976 #define BNX_TPAT_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
3977 #define BNX_TPAT_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
3978 #define BNX_TPAT_CPU_MODE_MSG_BIT1			 (1L<<6)
3979 #define BNX_TPAT_CPU_MODE_INTERRUPT_ENA		 (1L<<7)
3980 #define BNX_TPAT_CPU_MODE_SOFT_HALT			 (1L<<10)
3981 #define BNX_TPAT_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
3982 #define BNX_TPAT_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
3983 #define BNX_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
3984 #define BNX_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
3987 #define BNX_TPAT_CPU_STATE_BREAKPOINT			 (1L<<0)
3988 #define BNX_TPAT_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
3989 #define BNX_TPAT_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
3990 #define BNX_TPAT_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
3991 #define BNX_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED	 (1L<<5)
3992 #define BNX_TPAT_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
3993 #define BNX_TPAT_CPU_STATE_ALIGN_HALTED		 (1L<<7)
3994 #define BNX_TPAT_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
3995 #define BNX_TPAT_CPU_STATE_SOFT_HALTED			 (1L<<10)
3996 #define BNX_TPAT_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
3997 #define BNX_TPAT_CPU_STATE_INTERRRUPT			 (1L<<12)
3998 #define BNX_TPAT_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
3999 #define BNX_TPAT_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
4000 #define BNX_TPAT_CPU_STATE_BLOCKED_READ		 (1L<<31)
4003 #define BNX_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK	 (1L<<0)
4004 #define BNX_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4005 #define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4006 #define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4007 #define BNX_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4008 #define BNX_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4009 #define BNX_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4010 #define BNX_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4011 #define BNX_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
4012 #define BNX_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4013 #define BNX_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4022 #define BNX_TPAT_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4027 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4030 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4034 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4035 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP	 (0L<<1)
4036 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4043 #define BNX_TPAT_FTQ_CMD_WR_TOP			 (1L<<10)
4044 #define BNX_TPAT_FTQ_CMD_WR_TOP_0			 (0L<<10)
4045 #define BNX_TPAT_FTQ_CMD_WR_TOP_1			 (1L<<10)
4046 #define BNX_TPAT_FTQ_CMD_SFT_RESET			 (1L<<25)
4047 #define BNX_TPAT_FTQ_CMD_RD_DATA			 (1L<<26)
4048 #define BNX_TPAT_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
4049 #define BNX_TPAT_FTQ_CMD_ADD_DATA			 (1L<<28)
4050 #define BNX_TPAT_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
4051 #define BNX_TPAT_FTQ_CMD_POP				 (1L<<30)
4052 #define BNX_TPAT_FTQ_CMD_BUSY				 (1L<<31)
4055 #define BNX_TPAT_FTQ_CTL_INTERVENE			 (1L<<0)
4056 #define BNX_TPAT_FTQ_CTL_OVERFLOW			 (1L<<1)
4057 #define BNX_TPAT_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4069 #define BNX_RXP_CPU_MODE_LOCAL_RST			 (1L<<0)
4070 #define BNX_RXP_CPU_MODE_STEP_ENA			 (1L<<1)
4071 #define BNX_RXP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4072 #define BNX_RXP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4073 #define BNX_RXP_CPU_MODE_MSG_BIT1			 (1L<<6)
4074 #define BNX_RXP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
4075 #define BNX_RXP_CPU_MODE_SOFT_HALT			 (1L<<10)
4076 #define BNX_RXP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
4077 #define BNX_RXP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
4078 #define BNX_RXP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
4079 #define BNX_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4082 #define BNX_RXP_CPU_STATE_BREAKPOINT			 (1L<<0)
4083 #define BNX_RXP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
4084 #define BNX_RXP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
4085 #define BNX_RXP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
4086 #define BNX_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
4087 #define BNX_RXP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4088 #define BNX_RXP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
4089 #define BNX_RXP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
4090 #define BNX_RXP_CPU_STATE_SOFT_HALTED			 (1L<<10)
4091 #define BNX_RXP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
4092 #define BNX_RXP_CPU_STATE_INTERRRUPT			 (1L<<12)
4093 #define BNX_RXP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
4094 #define BNX_RXP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
4095 #define BNX_RXP_CPU_STATE_BLOCKED_READ			 (1L<<31)
4098 #define BNX_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4099 #define BNX_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4100 #define BNX_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4101 #define BNX_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4102 #define BNX_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4103 #define BNX_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4104 #define BNX_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4105 #define BNX_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4106 #define BNX_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
4107 #define BNX_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4108 #define BNX_RXP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4117 #define BNX_RXP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4122 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4125 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4129 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4130 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)
4131 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4138 #define BNX_RXP_CFTQ_CMD_WR_TOP			 (1L<<10)
4139 #define BNX_RXP_CFTQ_CMD_WR_TOP_0			 (0L<<10)
4140 #define BNX_RXP_CFTQ_CMD_WR_TOP_1			 (1L<<10)
4141 #define BNX_RXP_CFTQ_CMD_SFT_RESET			 (1L<<25)
4142 #define BNX_RXP_CFTQ_CMD_RD_DATA			 (1L<<26)
4143 #define BNX_RXP_CFTQ_CMD_ADD_INTERVEN			 (1L<<27)
4144 #define BNX_RXP_CFTQ_CMD_ADD_DATA			 (1L<<28)
4145 #define BNX_RXP_CFTQ_CMD_INTERVENE_CLR			 (1L<<29)
4146 #define BNX_RXP_CFTQ_CMD_POP				 (1L<<30)
4147 #define BNX_RXP_CFTQ_CMD_BUSY				 (1L<<31)
4150 #define BNX_RXP_CFTQ_CTL_INTERVENE			 (1L<<0)
4151 #define BNX_RXP_CFTQ_CTL_OVERFLOW			 (1L<<1)
4152 #define BNX_RXP_CFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4159 #define BNX_RXP_FTQ_CMD_WR_TOP				 (1L<<10)
4160 #define BNX_RXP_FTQ_CMD_WR_TOP_0			 (0L<<10)
4161 #define BNX_RXP_FTQ_CMD_WR_TOP_1			 (1L<<10)
4162 #define BNX_RXP_FTQ_CMD_SFT_RESET			 (1L<<25)
4163 #define BNX_RXP_FTQ_CMD_RD_DATA			 (1L<<26)
4164 #define BNX_RXP_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
4165 #define BNX_RXP_FTQ_CMD_ADD_DATA			 (1L<<28)
4166 #define BNX_RXP_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
4167 #define BNX_RXP_FTQ_CMD_POP				 (1L<<30)
4168 #define BNX_RXP_FTQ_CMD_BUSY				 (1L<<31)
4171 #define BNX_RXP_FTQ_CTL_INTERVENE			 (1L<<0)
4172 #define BNX_RXP_FTQ_CTL_OVERFLOW			 (1L<<1)
4173 #define BNX_RXP_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4185 #define BNX_COM_CPU_MODE_LOCAL_RST			 (1L<<0)
4186 #define BNX_COM_CPU_MODE_STEP_ENA			 (1L<<1)
4187 #define BNX_COM_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4188 #define BNX_COM_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4189 #define BNX_COM_CPU_MODE_MSG_BIT1			 (1L<<6)
4190 #define BNX_COM_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
4191 #define BNX_COM_CPU_MODE_SOFT_HALT			 (1L<<10)
4192 #define BNX_COM_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
4193 #define BNX_COM_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
4194 #define BNX_COM_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
4195 #define BNX_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4198 #define BNX_COM_CPU_STATE_BREAKPOINT			 (1L<<0)
4199 #define BNX_COM_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
4200 #define BNX_COM_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
4201 #define BNX_COM_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
4202 #define BNX_COM_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
4203 #define BNX_COM_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4204 #define BNX_COM_CPU_STATE_ALIGN_HALTED			 (1L<<7)
4205 #define BNX_COM_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
4206 #define BNX_COM_CPU_STATE_SOFT_HALTED			 (1L<<10)
4207 #define BNX_COM_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
4208 #define BNX_COM_CPU_STATE_INTERRRUPT			 (1L<<12)
4209 #define BNX_COM_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
4210 #define BNX_COM_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
4211 #define BNX_COM_CPU_STATE_BLOCKED_READ			 (1L<<31)
4214 #define BNX_COM_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4215 #define BNX_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4216 #define BNX_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4217 #define BNX_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4218 #define BNX_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4219 #define BNX_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4220 #define BNX_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4221 #define BNX_COM_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4222 #define BNX_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
4223 #define BNX_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4224 #define BNX_COM_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4233 #define BNX_COM_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4238 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4241 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4245 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4246 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)
4247 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4254 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP			 (1L<<10)
4255 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
4256 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
4257 #define BNX_COM_COMXQ_FTQ_CMD_SFT_RESET		 (1L<<25)
4258 #define BNX_COM_COMXQ_FTQ_CMD_RD_DATA			 (1L<<26)
4259 #define BNX_COM_COMXQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4260 #define BNX_COM_COMXQ_FTQ_CMD_ADD_DATA			 (1L<<28)
4261 #define BNX_COM_COMXQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4262 #define BNX_COM_COMXQ_FTQ_CMD_POP			 (1L<<30)
4263 #define BNX_COM_COMXQ_FTQ_CMD_BUSY			 (1L<<31)
4266 #define BNX_COM_COMXQ_FTQ_CTL_INTERVENE		 (1L<<0)
4267 #define BNX_COM_COMXQ_FTQ_CTL_OVERFLOW			 (1L<<1)
4268 #define BNX_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4275 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP			 (1L<<10)
4276 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
4277 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
4278 #define BNX_COM_COMTQ_FTQ_CMD_SFT_RESET		 (1L<<25)
4279 #define BNX_COM_COMTQ_FTQ_CMD_RD_DATA			 (1L<<26)
4280 #define BNX_COM_COMTQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4281 #define BNX_COM_COMTQ_FTQ_CMD_ADD_DATA			 (1L<<28)
4282 #define BNX_COM_COMTQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4283 #define BNX_COM_COMTQ_FTQ_CMD_POP			 (1L<<30)
4284 #define BNX_COM_COMTQ_FTQ_CMD_BUSY			 (1L<<31)
4287 #define BNX_COM_COMTQ_FTQ_CTL_INTERVENE		 (1L<<0)
4288 #define BNX_COM_COMTQ_FTQ_CTL_OVERFLOW			 (1L<<1)
4289 #define BNX_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4296 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP			 (1L<<10)
4297 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
4298 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
4299 #define BNX_COM_COMQ_FTQ_CMD_SFT_RESET			 (1L<<25)
4300 #define BNX_COM_COMQ_FTQ_CMD_RD_DATA			 (1L<<26)
4301 #define BNX_COM_COMQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4302 #define BNX_COM_COMQ_FTQ_CMD_ADD_DATA			 (1L<<28)
4303 #define BNX_COM_COMQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4304 #define BNX_COM_COMQ_FTQ_CMD_POP			 (1L<<30)
4305 #define BNX_COM_COMQ_FTQ_CMD_BUSY			 (1L<<31)
4308 #define BNX_COM_COMQ_FTQ_CTL_INTERVENE			 (1L<<0)
4309 #define BNX_COM_COMQ_FTQ_CTL_OVERFLOW			 (1L<<1)
4310 #define BNX_COM_COMQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4322 #define BNX_CP_CPU_MODE_LOCAL_RST			 (1L<<0)
4323 #define BNX_CP_CPU_MODE_STEP_ENA			 (1L<<1)
4324 #define BNX_CP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4325 #define BNX_CP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4326 #define BNX_CP_CPU_MODE_MSG_BIT1			 (1L<<6)
4327 #define BNX_CP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
4328 #define BNX_CP_CPU_MODE_SOFT_HALT			 (1L<<10)
4329 #define BNX_CP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
4330 #define BNX_CP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
4331 #define BNX_CP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
4332 #define BNX_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4335 #define BNX_CP_CPU_STATE_BREAKPOINT			 (1L<<0)
4336 #define BNX_CP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
4337 #define BNX_CP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
4338 #define BNX_CP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
4339 #define BNX_CP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
4340 #define BNX_CP_CPU_STATE_BAD_pc_HALTED			 (1L<<6)
4341 #define BNX_CP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
4342 #define BNX_CP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
4343 #define BNX_CP_CPU_STATE_SOFT_HALTED			 (1L<<10)
4344 #define BNX_CP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
4345 #define BNX_CP_CPU_STATE_INTERRRUPT			 (1L<<12)
4346 #define BNX_CP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
4347 #define BNX_CP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
4348 #define BNX_CP_CPU_STATE_BLOCKED_READ			 (1L<<31)
4351 #define BNX_CP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4352 #define BNX_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4353 #define BNX_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4354 #define BNX_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4355 #define BNX_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4356 #define BNX_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4357 #define BNX_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4358 #define BNX_CP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4359 #define BNX_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK		 (1L<<10)
4360 #define BNX_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4361 #define BNX_CP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4370 #define BNX_CP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4375 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4378 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4382 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4383 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)
4384 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4391 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP			 (1L<<10)
4392 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
4393 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
4394 #define BNX_CP_CPQ_FTQ_CMD_SFT_RESET			 (1L<<25)
4395 #define BNX_CP_CPQ_FTQ_CMD_RD_DATA			 (1L<<26)
4396 #define BNX_CP_CPQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4397 #define BNX_CP_CPQ_FTQ_CMD_ADD_DATA			 (1L<<28)
4398 #define BNX_CP_CPQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4399 #define BNX_CP_CPQ_FTQ_CMD_POP				 (1L<<30)
4400 #define BNX_CP_CPQ_FTQ_CMD_BUSY			 (1L<<31)
4403 #define BNX_CP_CPQ_FTQ_CTL_INTERVENE			 (1L<<0)
4404 #define BNX_CP_CPQ_FTQ_CTL_OVERFLOW			 (1L<<1)
4405 #define BNX_CP_CPQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4417 #define BNX_MCP_CPU_MODE_LOCAL_RST			 (1L<<0)
4418 #define BNX_MCP_CPU_MODE_STEP_ENA			 (1L<<1)
4419 #define BNX_MCP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4420 #define BNX_MCP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4421 #define BNX_MCP_CPU_MODE_MSG_BIT1			 (1L<<6)
4422 #define BNX_MCP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
4423 #define BNX_MCP_CPU_MODE_SOFT_HALT			 (1L<<10)
4424 #define BNX_MCP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
4425 #define BNX_MCP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
4426 #define BNX_MCP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
4427 #define BNX_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4430 #define BNX_MCP_CPU_STATE_BREAKPOINT			 (1L<<0)
4431 #define BNX_MCP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
4432 #define BNX_MCP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
4433 #define BNX_MCP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
4434 #define BNX_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
4435 #define BNX_MCP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4436 #define BNX_MCP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
4437 #define BNX_MCP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
4438 #define BNX_MCP_CPU_STATE_SOFT_HALTED			 (1L<<10)
4439 #define BNX_MCP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
4440 #define BNX_MCP_CPU_STATE_INTERRRUPT			 (1L<<12)
4441 #define BNX_MCP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
4442 #define BNX_MCP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
4443 #define BNX_MCP_CPU_STATE_BLOCKED_READ			 (1L<<31)
4446 #define BNX_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4447 #define BNX_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4448 #define BNX_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4449 #define BNX_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4450 #define BNX_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4451 #define BNX_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4452 #define BNX_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4453 #define BNX_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4454 #define BNX_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
4455 #define BNX_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4456 #define BNX_MCP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4465 #define BNX_MCP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4470 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4473 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4477 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4478 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)
4479 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4486 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP			 (1L<<10)
4487 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
4488 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
4489 #define BNX_MCP_MCPQ_FTQ_CMD_SFT_RESET			 (1L<<25)
4490 #define BNX_MCP_MCPQ_FTQ_CMD_RD_DATA			 (1L<<26)
4491 #define BNX_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4492 #define BNX_MCP_MCPQ_FTQ_CMD_ADD_DATA			 (1L<<28)
4493 #define BNX_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4494 #define BNX_MCP_MCPQ_FTQ_CMD_POP			 (1L<<30)
4495 #define BNX_MCP_MCPQ_FTQ_CMD_BUSY			 (1L<<31)
4498 #define BNX_MCP_MCPQ_FTQ_CTL_INTERVENE			 (1L<<0)
4499 #define BNX_MCP_MCPQ_FTQ_CTL_OVERFLOW			 (1L<<1)
4500 #define BNX_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)