Lines Matching defs:cpu_reg
349 void bnx_load_cpu_fw(struct bnx_softc *, struct cpu_reg *,
2806 bnx_load_cpu_fw(struct bnx_softc *sc, struct cpu_reg *cpu_reg,
2813 val = REG_RD_IND(sc, cpu_reg->mode);
2814 val |= cpu_reg->mode_value_halt;
2815 REG_WR_IND(sc, cpu_reg->mode, val);
2816 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2819 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2828 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2837 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2846 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2855 offset = cpu_reg->spad_base +
2856 (fw->rodata_addr - cpu_reg->mips_view_base);
2865 REG_WR_IND(sc, cpu_reg->inst, 0);
2866 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2869 val = REG_RD_IND(sc, cpu_reg->mode);
2870 val &= ~cpu_reg->mode_value_halt;
2871 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2872 REG_WR_IND(sc, cpu_reg->mode, val);
2888 struct cpu_reg cpu_reg;
2906 cpu_reg.mode = BNX_RXP_CPU_MODE;
2907 cpu_reg.mode_value_halt = BNX_RXP_CPU_MODE_SOFT_HALT;
2908 cpu_reg.mode_value_sstep = BNX_RXP_CPU_MODE_STEP_ENA;
2909 cpu_reg.state = BNX_RXP_CPU_STATE;
2910 cpu_reg.state_value_clear = 0xffffff;
2911 cpu_reg.gpr0 = BNX_RXP_CPU_REG_FILE;
2912 cpu_reg.evmask = BNX_RXP_CPU_EVENT_MASK;
2913 cpu_reg.pc = BNX_RXP_CPU_PROGRAM_COUNTER;
2914 cpu_reg.inst = BNX_RXP_CPU_INSTRUCTION;
2915 cpu_reg.bp = BNX_RXP_CPU_HW_BREAKPOINT;
2916 cpu_reg.spad_base = BNX_RXP_SCRATCH;
2917 cpu_reg.mips_view_base = 0x8000000;
2950 bnx_load_cpu_fw(sc, &cpu_reg, &fw);
2953 cpu_reg.mode = BNX_TXP_CPU_MODE;
2954 cpu_reg.mode_value_halt = BNX_TXP_CPU_MODE_SOFT_HALT;
2955 cpu_reg.mode_value_sstep = BNX_TXP_CPU_MODE_STEP_ENA;
2956 cpu_reg.state = BNX_TXP_CPU_STATE;
2957 cpu_reg.state_value_clear = 0xffffff;
2958 cpu_reg.gpr0 = BNX_TXP_CPU_REG_FILE;
2959 cpu_reg.evmask = BNX_TXP_CPU_EVENT_MASK;
2960 cpu_reg.pc = BNX_TXP_CPU_PROGRAM_COUNTER;
2961 cpu_reg.inst = BNX_TXP_CPU_INSTRUCTION;
2962 cpu_reg.bp = BNX_TXP_CPU_HW_BREAKPOINT;
2963 cpu_reg.spad_base = BNX_TXP_SCRATCH;
2964 cpu_reg.mips_view_base = 0x8000000;
2997 bnx_load_cpu_fw(sc, &cpu_reg, &fw);
3000 cpu_reg.mode = BNX_TPAT_CPU_MODE;
3001 cpu_reg.mode_value_halt = BNX_TPAT_CPU_MODE_SOFT_HALT;
3002 cpu_reg.mode_value_sstep = BNX_TPAT_CPU_MODE_STEP_ENA;
3003 cpu_reg.state = BNX_TPAT_CPU_STATE;
3004 cpu_reg.state_value_clear = 0xffffff;
3005 cpu_reg.gpr0 = BNX_TPAT_CPU_REG_FILE;
3006 cpu_reg.evmask = BNX_TPAT_CPU_EVENT_MASK;
3007 cpu_reg.pc = BNX_TPAT_CPU_PROGRAM_COUNTER;
3008 cpu_reg.inst = BNX_TPAT_CPU_INSTRUCTION;
3009 cpu_reg.bp = BNX_TPAT_CPU_HW_BREAKPOINT;
3010 cpu_reg.spad_base = BNX_TPAT_SCRATCH;
3011 cpu_reg.mips_view_base = 0x8000000;
3044 bnx_load_cpu_fw(sc, &cpu_reg, &fw);
3047 cpu_reg.mode = BNX_COM_CPU_MODE;
3048 cpu_reg.mode_value_halt = BNX_COM_CPU_MODE_SOFT_HALT;
3049 cpu_reg.mode_value_sstep = BNX_COM_CPU_MODE_STEP_ENA;
3050 cpu_reg.state = BNX_COM_CPU_STATE;
3051 cpu_reg.state_value_clear = 0xffffff;
3052 cpu_reg.gpr0 = BNX_COM_CPU_REG_FILE;
3053 cpu_reg.evmask = BNX_COM_CPU_EVENT_MASK;
3054 cpu_reg.pc = BNX_COM_CPU_PROGRAM_COUNTER;
3055 cpu_reg.inst = BNX_COM_CPU_INSTRUCTION;
3056 cpu_reg.bp = BNX_COM_CPU_HW_BREAKPOINT;
3057 cpu_reg.spad_base = BNX_COM_SCRATCH;
3058 cpu_reg.mips_view_base = 0x8000000;
3091 bnx_load_cpu_fw(sc, &cpu_reg, &fw);