Lines Matching defs:sc
167 struct alc_softc *sc = (struct alc_softc *)dev;
170 if (phy != sc->alc_phyaddr)
173 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
184 struct alc_softc *sc = (struct alc_softc *)dev;
194 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 &&
198 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
202 v = CSR_READ_4(sc, ALC_MDIO);
209 sc->sc_dev.dv_xname, phy, reg);
219 struct alc_softc *sc = (struct alc_softc *)dev;
223 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
227 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
231 v = CSR_READ_4(sc, ALC_MDIO);
238 sc->sc_dev.dv_xname, phy, reg);
248 struct alc_softc *sc = (struct alc_softc *)dev;
250 if (phy != sc->alc_phyaddr)
253 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
262 struct alc_softc *sc = (struct alc_softc *)dev;
266 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
271 v = CSR_READ_4(sc, ALC_MDIO);
278 sc->sc_dev.dv_xname, phy, reg);
284 struct alc_softc *sc = (struct alc_softc *)dev;
288 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
292 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
297 v = CSR_READ_4(sc, ALC_MDIO);
304 sc->sc_dev.dv_xname, phy, reg);
310 struct alc_softc *sc = (struct alc_softc *)dev;
311 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
312 struct mii_data *mii = &sc->sc_miibus;
318 sc->alc_flags &= ~ALC_FLAG_LINK;
324 sc->alc_flags |= ALC_FLAG_LINK;
327 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
328 sc->alc_flags |= ALC_FLAG_LINK;
335 alc_stop_mac(sc);
338 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
339 alc_start_queue(sc);
340 alc_mac_config(sc);
342 reg = CSR_READ_4(sc, ALC_MAC_CFG);
344 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
346 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active));
347 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active));
351 alc_miidbg_readreg(struct alc_softc *sc, int reg)
353 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
355 return (alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
361 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val)
363 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
365 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
370 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg)
375 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
377 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
381 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
385 v = CSR_READ_4(sc, ALC_MDIO);
392 sc->sc_dev.dv_xname, devaddr, reg);
400 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val)
405 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
407 if ((sc->alc_flags & ALC_FLAG_LINK) != 0)
411 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
416 v = CSR_READ_4(sc, ALC_MDIO);
423 sc->sc_dev.dv_xname, devaddr, reg);
427 alc_dsp_fixup(struct alc_softc *sc, int media)
431 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
433 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0)
440 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
441 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6);
444 agc = alc_miidbg_readreg(sc, MII_DBG_AGC);
450 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
452 val = alc_miiext_readreg(sc, MII_EXT_ANEG,
455 alc_miiext_writereg(sc, MII_EXT_ANEG,
458 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT,
460 val = alc_miiext_readreg(sc, MII_EXT_ANEG,
463 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE,
466 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
467 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
473 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
477 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
479 alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
483 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE);
485 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val);
486 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 &&
487 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) {
488 alc_miidbg_writereg(sc, MII_DBG_MSE16DB,
490 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB);
493 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val);
501 struct alc_softc *sc = ifp->if_softc;
502 struct mii_data *mii = &sc->sc_miibus;
515 struct alc_softc *sc = ifp->if_softc;
516 struct mii_data *mii = &sc->sc_miibus;
538 alc_get_macaddr(struct alc_softc *sc)
540 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
541 alc_get_macaddr_816x(sc);
543 alc_get_macaddr_813x(sc);
547 alc_get_macaddr_813x(struct alc_softc *sc)
554 opt = CSR_READ_4(sc, ALC_OPT_CFG);
555 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
556 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
562 switch (sc->sc_product) {
567 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
568 CSR_READ_4(sc, ALC_OPT_CFG);
576 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
578 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
580 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
582 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
584 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
586 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
592 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
593 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
594 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
595 CSR_READ_4(sc, ALC_WOL_CFG);
597 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
601 if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
607 sc->sc_dev.dv_xname);
610 printf("%s: EEPROM not found!\n", sc->sc_dev.dv_xname);
613 switch (sc->sc_product) {
618 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
619 CSR_READ_4(sc, ALC_OPT_CFG);
627 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
629 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
631 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
633 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
635 val = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
637 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
644 alc_get_macaddr_par(sc);
648 alc_get_macaddr_816x(struct alc_softc *sc)
656 reg = CSR_READ_4(sc, ALC_SLD);
662 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);
665 reg = CSR_READ_4(sc, ALC_SLD);
673 "out!\n", sc->sc_dev.dv_xname);
678 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
682 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
689 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |
693 reg = CSR_READ_4(sc, ALC_EEPROM_LD);
699 sc->sc_dev.dv_xname);
703 alc_get_macaddr_par(sc);
707 alc_get_macaddr_par(struct alc_softc *sc)
711 ea[0] = CSR_READ_4(sc, ALC_PAR0);
712 ea[1] = CSR_READ_4(sc, ALC_PAR1);
713 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
714 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
715 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
716 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
717 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
718 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
722 alc_disable_l0s_l1(struct alc_softc *sc)
726 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
728 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
734 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
739 alc_phy_reset(struct alc_softc *sc)
741 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
742 alc_phy_reset_816x(sc);
744 alc_phy_reset_813x(sc);
748 alc_phy_reset_813x(struct alc_softc *sc)
753 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET);
754 CSR_READ_2(sc, ALC_GPHY_CFG);
757 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
759 CSR_READ_2(sc, ALC_GPHY_CFG);
763 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) {
764 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
766 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
768 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
771 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
772 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
773 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
774 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) {
775 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
777 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
779 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
783 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D) {
784 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
786 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
789 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C ||
790 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C ||
791 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
792 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) {
793 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
795 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
802 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
804 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
810 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
812 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
820 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
822 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
829 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
831 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
837 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
839 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
844 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
846 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
849 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
852 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR,
854 data = alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr,
857 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA,
862 alc_phy_reset_816x(struct alc_softc *sc)
866 val = CSR_READ_4(sc, ALC_GPHY_CFG);
873 CSR_WRITE_4(sc, ALC_GPHY_CFG, val);
875 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET);
879 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS,
881 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, DBG_HIBNEG_DEFAULT &
883 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT);
885 val = CSR_READ_4(sc, ALC_LPI_CTL);
887 CSR_WRITE_4(sc, ALC_LPI_CTL, val);
888 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0);
890 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT);
891 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT);
892 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT);
893 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT);
894 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
896 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
898 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78,
900 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10,
902 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) {
904 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3);
906 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val);
908 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2);
910 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val);
912 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5);
914 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val);
919 alc_phy_down(struct alc_softc *sc)
923 switch (sc->sc_product) {
931 gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
937 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
954 alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr,
959 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
968 alc_aspm(struct alc_softc *sc, int init, uint64_t media)
970 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
971 alc_aspm_816x(sc, init);
973 alc_aspm_813x(sc, media);
977 alc_aspm_813x(struct alc_softc *sc, uint64_t media)
982 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
983 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) ==
985 linkcfg = CSR_READ_2(sc, sc->alc_expcap + PCI_PCIE_LCSR);
994 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
997 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
998 sc->alc_rev == ATHEROS_AR8152_B_V10)
1000 CSR_WRITE_2(sc, sc->alc_expcap + PCI_PCIE_LCSR, linkcfg);
1011 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1012 if ((sc->alc_flags & ALC_FLAG_L0S) != 0)
1014 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1016 if ((sc->alc_flags & ALC_FLAG_APS) != 0) {
1017 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1)
1025 switch (sc->sc_product) {
1052 if ((sc->alc_flags & ALC_FLAG_L1S) != 0)
1055 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1059 alc_aspm_816x(struct alc_softc *sc, int init)
1061 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1064 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1077 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
1078 (sc->alc_rev & 0x01) != 0)
1080 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) {
1091 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1095 alc_init_pcie(struct alc_softc *sc, int base)
1102 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
1104 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
1106 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
1107 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
1108 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
1109 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
1110 CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
1112 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 &&
1113 sc->alc_rev == ATHEROS_AR8152_B_V10) {
1114 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
1119 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
1122 cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
1125 ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag,
1128 sc->alc_rcb = DMA_CFG_RCB_128;
1131 sc->sc_dev.dv_xname,
1132 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128);
1135 sc->alc_flags |= ALC_FLAG_L0S;
1137 sc->alc_flags |= ALC_FLAG_L1S;
1140 sc->sc_dev.dv_xname,
1143 alc_disable_l0s_l1(sc);
1146 val = CSR_READ_4(sc, ALC_PDLL_TRNS1);
1148 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val);
1149 val = CSR_READ_4(sc, ALC_MASTER_CFG);
1150 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
1151 (sc->alc_rev & 0x01) != 0) {
1155 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1162 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1169 alc_config_msi(struct alc_softc *sc)
1173 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
1180 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER);
1183 mod = ALC_USECS(sc->alc_int_rx_mod);
1187 if ((sc->alc_flags & ALC_FLAG_MSI) != 0)
1188 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl |
1191 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0);
1198 struct alc_softc *sc = (struct alc_softc *)self;
1209 sc->alc_phyaddr = ALC_PHY_ADDR;
1212 sc->sc_product = PCI_PRODUCT(pa->pa_id);
1213 sc->alc_rev = PCI_REVISION(pa->pa_class);
1222 switch (sc->sc_product) {
1226 sc->alc_flags |= ALC_FLAG_E2X00;
1229 if (AR816X_REV(sc->alc_rev) == 0)
1230 sc->alc_flags |= ALC_FLAG_LINK_WAR;
1233 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY;
1237 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY;
1241 sc->alc_flags |= ALC_FLAG_APS;
1244 sc->alc_flags |= ALC_FLAG_FASTETHER;
1248 sc->alc_flags |= ALC_FLAG_APS;
1253 sc->alc_flags |= ALC_FLAG_JUMBO;
1259 if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt,
1260 &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) {
1265 sc->alc_flags |= ALC_FLAG_MSI;
1271 sc->alc_flags &= ~ALC_FLAG_MSI;
1278 sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc,
1279 sc->sc_dev.dv_xname);
1280 if (sc->sc_irq_handle == NULL) {
1289 alc_config_msi(sc);
1291 sc->sc_dmat = pa->pa_dmat;
1292 sc->sc_pct = pa->pa_pc;
1293 sc->sc_pcitag = pa->pa_tag;
1295 switch (sc->sc_product) {
1300 sc->alc_max_framelen = 6 * 1024;
1303 sc->alc_max_framelen = 9 * 1024;
1313 sc->alc_flags |= ALC_FLAG_SMB_BUG;
1317 sc->alc_flags |= ALC_FLAG_CMB_BUG;
1318 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
1322 sc->sc_dev.dv_xname, sc->alc_rev);
1324 sc->sc_dev.dv_xname, sc->alc_chip_rev);
1325 printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname,
1326 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
1327 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
1331 sc->alc_dma_rd_burst = 0;
1332 sc->alc_dma_wr_burst = 0;
1333 sc->alc_rcb = DMA_CFG_RCB_64;
1336 sc->alc_flags |= ALC_FLAG_PCIE;
1337 sc->alc_expcap = base;
1338 burst = CSR_READ_2(sc, base + PCI_PCIE_DCSR);
1339 sc->alc_dma_rd_burst = (burst & 0x7000) >> 12;
1340 sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5;
1343 sc->sc_dev.dv_xname,
1344 alc_dma_burst[sc->alc_dma_rd_burst]);
1346 sc->sc_dev.dv_xname,
1347 alc_dma_burst[sc->alc_dma_wr_burst]);
1349 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024)
1350 sc->alc_dma_rd_burst = 3;
1351 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024)
1352 sc->alc_dma_wr_burst = 3;
1358 if ((sc->alc_flags &
1360 sc->alc_dma_wr_burst = 0;
1361 alc_init_pcie(sc, base);
1365 alc_phy_reset(sc);
1368 alc_stop_mac(sc);
1369 alc_reset(sc);
1371 error = alc_dma_alloc(sc);
1376 alc_get_macaddr(sc);
1378 ifp = &sc->sc_arpcom.ac_if;
1379 ifp->if_softc = sc;
1385 bcopy(sc->alc_eaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
1386 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
1399 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
1402 sc->sc_miibus.mii_ifp = ifp;
1403 sc->sc_miibus.mii_readreg = alc_miibus_readreg;
1404 sc->sc_miibus.mii_writereg = alc_miibus_writereg;
1405 sc->sc_miibus.mii_statchg = alc_miibus_statchg;
1407 ifmedia_init(&sc->sc_miibus.mii_media, 0, alc_mediachange,
1409 mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY,
1412 if (LIST_FIRST(&sc->sc_miibus.mii_phys) == NULL) {
1413 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname);
1414 ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL,
1416 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL);
1418 ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO);
1423 timeout_set(&sc->alc_tick_ch, alc_tick, sc);
1427 alc_dma_free(sc);
1428 if (sc->sc_irq_handle != NULL)
1429 pci_intr_disestablish(pc, sc->sc_irq_handle);
1430 if (sc->sc_mem_size)
1431 bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size);
1437 struct alc_softc *sc = (struct alc_softc *)self;
1438 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1442 alc_stop(sc);
1445 mii_detach(&sc->sc_miibus, MII_PHY_ANY, MII_OFFSET_ANY);
1448 ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY);
1452 alc_dma_free(sc);
1454 alc_phy_down(sc);
1455 if (sc->sc_irq_handle != NULL) {
1456 pci_intr_disestablish(sc->sc_pct, sc->sc_irq_handle);
1457 sc->sc_irq_handle = NULL;
1466 struct alc_softc *sc = (struct alc_softc *)self;
1467 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1472 alc_stop(sc);
1483 alc_dma_alloc(struct alc_softc *sc)
1492 error = bus_dmamap_create(sc->sc_dmat, ALC_TX_RING_SZ, 1,
1493 ALC_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_tx_ring_map);
1498 error = bus_dmamem_alloc(sc->sc_dmat, ALC_TX_RING_SZ,
1499 ETHER_ALIGN, 0, &sc->alc_rdata.alc_tx_ring_seg, 1,
1503 sc->sc_dev.dv_xname);
1507 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_tx_ring_seg,
1508 nsegs, ALC_TX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_tx_ring,
1514 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map,
1515 sc->alc_rdata.alc_tx_ring, ALC_TX_RING_SZ, NULL, BUS_DMA_WAITOK);
1518 sc->sc_dev.dv_xname);
1519 bus_dmamem_free(sc->sc_dmat,
1520 (bus_dma_segment_t *)&sc->alc_rdata.alc_tx_ring, 1);
1524 sc->alc_rdata.alc_tx_ring_paddr =
1525 sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr;
1530 error = bus_dmamap_create(sc->sc_dmat, ALC_RX_RING_SZ, 1,
1531 ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map);
1536 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ,
1537 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1,
1541 sc->sc_dev.dv_xname);
1545 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rx_ring_seg,
1546 nsegs, ALC_RX_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rx_ring,
1552 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map,
1553 sc->alc_rdata.alc_rx_ring, ALC_RX_RING_SZ, NULL, BUS_DMA_WAITOK);
1556 sc->sc_dev.dv_xname);
1557 bus_dmamem_free(sc->sc_dmat,
1558 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1);
1562 sc->alc_rdata.alc_rx_ring_paddr =
1563 sc->alc_cdata.alc_rx_ring_map->dm_segs[0].ds_addr;
1568 error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1,
1569 ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map);
1574 error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ,
1575 ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1,
1579 "return ring.\n", sc->sc_dev.dv_xname);
1583 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_rr_ring_seg,
1584 nsegs, ALC_RR_RING_SZ, (caddr_t *)&sc->alc_rdata.alc_rr_ring,
1590 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map,
1591 sc->alc_rdata.alc_rr_ring, ALC_RR_RING_SZ, NULL, BUS_DMA_WAITOK);
1594 "\n", sc->sc_dev.dv_xname);
1595 bus_dmamem_free(sc->sc_dmat,
1596 (bus_dma_segment_t *)&sc->alc_rdata.alc_rr_ring, 1);
1600 sc->alc_rdata.alc_rr_ring_paddr =
1601 sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr;
1606 error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1,
1608 &sc->alc_cdata.alc_cmb_map);
1613 error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ,
1614 ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1,
1618 "CMB block\n", sc->sc_dev.dv_xname);
1622 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_cmb_seg,
1623 nsegs, ALC_CMB_SZ, (caddr_t *)&sc->alc_rdata.alc_cmb,
1629 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map,
1630 sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL,
1634 sc->sc_dev.dv_xname);
1635 bus_dmamem_free(sc->sc_dmat,
1636 (bus_dma_segment_t *)&sc->alc_rdata.alc_cmb, 1);
1640 sc->alc_rdata.alc_cmb_paddr =
1641 sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr;
1646 error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1,
1648 &sc->alc_cdata.alc_smb_map);
1653 error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ,
1654 ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1,
1658 "SMB block\n", sc->sc_dev.dv_xname);
1662 error = bus_dmamem_map(sc->sc_dmat, &sc->alc_rdata.alc_smb_seg,
1663 nsegs, ALC_SMB_SZ, (caddr_t *)&sc->alc_rdata.alc_smb,
1669 error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map,
1670 sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL,
1674 sc->sc_dev.dv_xname);
1675 bus_dmamem_free(sc->sc_dmat,
1676 (bus_dma_segment_t *)&sc->alc_rdata.alc_smb, 1);
1680 sc->alc_rdata.alc_smb_paddr =
1681 sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr;
1686 txd = &sc->alc_cdata.alc_txdesc[i];
1689 error = bus_dmamap_create(sc->sc_dmat, ALC_TSO_MAXSIZE,
1694 sc->sc_dev.dv_xname);
1700 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
1701 BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_sparemap);
1704 sc->sc_dev.dv_xname);
1709 rxd = &sc->alc_cdata.alc_rxdesc[i];
1712 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
1716 sc->sc_dev.dv_xname);
1725 alc_dma_free(struct alc_softc *sc)
1733 txd = &sc->alc_cdata.alc_txdesc[i];
1735 bus_dmamap_destroy(sc->sc_dmat, txd->tx_dmamap);
1741 rxd = &sc->alc_cdata.alc_rxdesc[i];
1743 bus_dmamap_destroy(sc->sc_dmat, rxd->rx_dmamap);
1747 if (sc->alc_cdata.alc_rx_sparemap != NULL) {
1748 bus_dmamap_destroy(sc->sc_dmat, sc->alc_cdata.alc_rx_sparemap);
1749 sc->alc_cdata.alc_rx_sparemap = NULL;
1753 if (sc->alc_cdata.alc_tx_ring_map != NULL)
1754 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map);
1755 if (sc->alc_cdata.alc_tx_ring_map != NULL &&
1756 sc->alc_rdata.alc_tx_ring != NULL)
1757 bus_dmamem_free(sc->sc_dmat,
1758 (bus_dma_segment_t *)sc->alc_rdata.alc_tx_ring, 1);
1759 sc->alc_rdata.alc_tx_ring = NULL;
1760 sc->alc_cdata.alc_tx_ring_map = NULL;
1763 if (sc->alc_cdata.alc_rx_ring_map != NULL)
1764 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map);
1765 if (sc->alc_cdata.alc_rx_ring_map != NULL &&
1766 sc->alc_rdata.alc_rx_ring != NULL)
1767 bus_dmamem_free(sc->sc_dmat,
1768 (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1);
1769 sc->alc_rdata.alc_rx_ring = NULL;
1770 sc->alc_cdata.alc_rx_ring_map = NULL;
1773 if (sc->alc_cdata.alc_rr_ring_map != NULL)
1774 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map);
1775 if (sc->alc_cdata.alc_rr_ring_map != NULL &&
1776 sc->alc_rdata.alc_rr_ring != NULL)
1777 bus_dmamem_free(sc->sc_dmat,
1778 (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1);
1779 sc->alc_rdata.alc_rr_ring = NULL;
1780 sc->alc_cdata.alc_rr_ring_map = NULL;
1783 if (sc->alc_cdata.alc_cmb_map != NULL)
1784 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_cmb_map);
1785 if (sc->alc_cdata.alc_cmb_map != NULL &&
1786 sc->alc_rdata.alc_cmb != NULL)
1787 bus_dmamem_free(sc->sc_dmat,
1788 (bus_dma_segment_t *)sc->alc_rdata.alc_cmb, 1);
1789 sc->alc_rdata.alc_cmb = NULL;
1790 sc->alc_cdata.alc_cmb_map = NULL;
1793 if (sc->alc_cdata.alc_smb_map != NULL)
1794 bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map);
1795 if (sc->alc_cdata.alc_smb_map != NULL &&
1796 sc->alc_rdata.alc_smb != NULL)
1797 bus_dmamem_free(sc->sc_dmat,
1798 (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1);
1799 sc->alc_rdata.alc_smb = NULL;
1800 sc->alc_cdata.alc_smb_map = NULL;
1804 alc_encap(struct alc_softc *sc, struct mbuf *m)
1815 prod = sc->alc_cdata.alc_tx_prod;
1816 txd = &sc->alc_cdata.alc_txdesc[prod];
1820 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT);
1828 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
1834 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1856 desc = &sc->alc_rdata.alc_tx_ring[prod];
1861 sc->alc_cdata.alc_tx_cnt++;
1866 sc->alc_cdata.alc_tx_prod = prod;
1870 desc = &sc->alc_rdata.alc_tx_ring[prod];
1874 txd = &sc->alc_cdata.alc_txdesc[prod];
1890 struct alc_softc *sc = ifp->if_softc;
1895 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT)
1896 alc_txeof(sc);
1900 if ((sc->alc_flags & ALC_FLAG_LINK) == 0)
1906 if (sc->alc_cdata.alc_tx_cnt + ALC_MAXTXSEGS >=
1916 if (alc_encap(sc, m) != 0) {
1934 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
1935 sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
1938 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
1939 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX,
1940 (uint16_t)sc->alc_cdata.alc_tx_prod);
1942 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
1943 (sc->alc_cdata.alc_tx_prod <<
1954 struct alc_softc *sc = ifp->if_softc;
1956 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) {
1958 sc->sc_dev.dv_xname);
1964 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
1973 struct alc_softc *sc = ifp->if_softc;
1974 struct mii_data *mii = &sc->sc_miibus;
1995 alc_stop(sc);
2005 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data);
2011 alc_iff(sc);
2020 alc_mac_config(struct alc_softc *sc)
2025 mii = &sc->sc_miibus;
2026 reg = CSR_READ_4(sc, ALC_MAC_CFG);
2029 if ((sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
2030 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
2031 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2 ||
2032 sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
2051 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2055 alc_stats_clear(struct alc_softc *sc)
2061 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2062 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
2063 sc->alc_cdata.alc_smb_map->dm_mapsize,
2065 smb = sc->alc_rdata.alc_smb;
2068 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
2069 sc->alc_cdata.alc_smb_map->dm_mapsize,
2074 CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2080 CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2087 alc_stats_update(struct alc_softc *sc)
2089 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
2095 stat = &sc->alc_stats;
2096 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2097 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
2098 sc->alc_cdata.alc_smb_map->dm_mapsize,
2100 smb = sc->alc_rdata.alc_smb;
2108 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2114 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2184 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) {
2187 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
2188 sc->alc_cdata.alc_smb_map->dm_mapsize,
2196 struct alc_softc *sc = arg;
2197 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
2201 status = CSR_READ_4(sc, ALC_INTR_STATUS);
2206 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT);
2208 status = CSR_READ_4(sc, ALC_INTR_STATUS);
2213 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
2219 error = alc_rxintr(sc);
2229 sc->sc_dev.dv_xname);
2232 sc->sc_dev.dv_xname);
2235 sc->sc_dev.dv_xname);
2240 alc_txeof(sc);
2247 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
2252 alc_txeof(struct alc_softc *sc)
2254 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
2259 if (sc->alc_cdata.alc_tx_cnt == 0)
2261 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
2262 sc->alc_cdata.alc_tx_ring_map->dm_mapsize,
2264 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
2265 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
2266 sc->alc_cdata.alc_cmb_map->dm_mapsize,
2268 prod = sc->alc_rdata.alc_cmb->cons;
2270 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
2271 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX);
2273 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
2279 cons = sc->alc_cdata.alc_tx_cons;
2286 if (sc->alc_cdata.alc_tx_cnt <= 0)
2290 sc->alc_cdata.alc_tx_cnt--;
2291 txd = &sc->alc_cdata.alc_txdesc[cons];
2294 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0,
2296 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap);
2302 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
2303 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
2304 sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_PREREAD);
2305 sc->alc_cdata.alc_tx_cons = cons;
2310 if (sc->alc_cdata.alc_tx_cnt == 0)
2315 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd)
2332 error = bus_dmamap_load_mbuf(sc->sc_dmat,
2333 sc->alc_cdata.alc_rx_sparemap, m, BUS_DMA_NOWAIT);
2337 printf("%s: can't load RX mbuf\n", sc->sc_dev.dv_xname);
2342 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0,
2344 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap);
2347 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap;
2348 sc->alc_cdata.alc_rx_sparemap = map;
2349 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize,
2357 alc_rxintr(struct alc_softc *sc)
2359 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
2364 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0,
2365 sc->alc_cdata.alc_rr_ring_map->dm_mapsize,
2367 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0,
2368 sc->alc_cdata.alc_rx_ring_map->dm_mapsize,
2370 rr_cons = sc->alc_cdata.alc_rr_cons;
2372 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons];
2381 "resetting\n", sc->sc_dev.dv_xname);
2384 alc_rxeof(sc, rrd);
2388 sc->alc_cdata.alc_rx_cons += nsegs;
2389 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT;
2395 sc->alc_cdata.alc_rr_cons = rr_cons;
2397 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0,
2398 sc->alc_cdata.alc_rr_ring_map->dm_mapsize,
2404 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0,
2405 sc->alc_cdata.alc_rx_ring_map->dm_mapsize,
2417 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
2418 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX,
2419 (uint16_t)sc->alc_cdata.alc_rx_cons);
2421 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
2422 sc->alc_cdata.alc_rx_cons);
2430 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd)
2432 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
2444 sc->alc_cdata.alc_rxlen = RRD_BYTES(status);
2465 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons];
2468 if (alc_newbuf(sc, rxd) != 0) {
2471 m_freem(sc->alc_cdata.alc_rxhead);
2480 mp->m_len = sc->alc_buf_size;
2483 if (sc->alc_cdata.alc_rxhead == NULL) {
2484 sc->alc_cdata.alc_rxhead = mp;
2485 sc->alc_cdata.alc_rxtail = mp;
2488 sc->alc_cdata.alc_rxprev_tail =
2489 sc->alc_cdata.alc_rxtail;
2490 sc->alc_cdata.alc_rxtail->m_next = mp;
2491 sc->alc_cdata.alc_rxtail = mp;
2496 m = sc->alc_cdata.alc_rxhead;
2503 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN;
2506 mp->m_len = sc->alc_cdata.alc_rxlen -
2507 (nsegs - 1) * sc->alc_buf_size;
2510 sc->alc_cdata.alc_rxtail =
2511 sc->alc_cdata.alc_rxprev_tail;
2512 sc->alc_cdata.alc_rxtail->m_len -=
2514 sc->alc_cdata.alc_rxtail->m_next = NULL;
2540 ALC_RXCHAIN_RESET(sc);
2546 struct alc_softc *sc = xsc;
2547 struct mii_data *mii = &sc->sc_miibus;
2552 alc_stats_update(sc);
2554 timeout_add_sec(&sc->alc_tick_ch, 1);
2559 alc_osc_reset(struct alc_softc *sc)
2563 reg = CSR_READ_4(sc, ALC_MISC3);
2566 CSR_WRITE_4(sc, ALC_MISC3, reg);
2567 reg = CSR_READ_4(sc, ALC_MISC);
2568 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) {
2576 CSR_WRITE_4(sc, ALC_MISC, reg);
2577 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
2578 reg = CSR_READ_4(sc, ALC_MISC2);
2580 CSR_WRITE_4(sc, ALC_MISC2, reg);
2581 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);
2585 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
2587 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
2588 CSR_WRITE_4(sc, ALC_MISC, reg);
2594 alc_reset(struct alc_softc *sc)
2599 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2601 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1);
2602 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
2603 (sc->alc_rev & 0x01) != 0) {
2605 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
2610 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
2614 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
2616 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2618 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2621 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)
2629 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
2633 printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname);
2636 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
2644 printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname,
2647 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2648 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 &&
2649 (sc->alc_rev & 0x01) != 0) {
2650 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
2652 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2656 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
2658 alc_osc_reset(sc);
2659 reg = CSR_READ_4(sc, ALC_MISC3);
2662 CSR_WRITE_4(sc, ALC_MISC3, reg);
2663 reg = CSR_READ_4(sc, ALC_MISC);
2665 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1)
2667 CSR_WRITE_4(sc, ALC_MISC, reg);
2670 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
2671 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
2672 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
2673 CSR_WRITE_4(sc, ALC_SERDES_LOCK,
2674 CSR_READ_4(sc, ALC_SERDES_LOCK) |
2681 struct alc_softc *sc = ifp->if_softc;
2690 alc_stop(sc);
2694 alc_reset(sc);
2697 error = alc_init_rx_ring(sc);
2699 printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname);
2700 alc_stop(sc);
2703 alc_init_rr_ring(sc);
2704 alc_init_tx_ring(sc);
2705 alc_init_cmb(sc);
2706 alc_init_smb(sc);
2709 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2710 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB |
2714 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0)
2715 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER,
2718 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
2722 CSR_WRITE_4(sc, ALC_PAR0,
2724 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
2729 CSR_READ_4(sc, ALC_WOL_CFG);
2730 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2732 paddr = sc->alc_rdata.alc_tx_ring_paddr;
2733 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2734 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2736 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
2738 CSR_WRITE_4(sc, ALC_TD_RING_CNT,
2741 paddr = sc->alc_rdata.alc_rx_ring_paddr;
2742 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2743 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2744 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
2746 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
2747 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
2748 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
2751 CSR_WRITE_4(sc, ALC_RD_RING_CNT,
2764 sc->alc_buf_size = RX_BUF_SIZE_MAX;
2765 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
2767 paddr = sc->alc_rdata.alc_rr_ring_paddr;
2769 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2770 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
2772 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
2773 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
2774 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
2777 CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
2779 paddr = sc->alc_rdata.alc_cmb_paddr;
2780 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
2781 paddr = sc->alc_rdata.alc_smb_paddr;
2782 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2783 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
2785 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) {
2787 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
2788 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
2789 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
2790 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
2791 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
2792 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
2793 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
2794 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
2798 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
2801 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT;
2802 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT;
2803 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT;
2804 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0)
2805 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT;
2806 CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
2811 reg = CSR_READ_4(sc, ALC_MASTER_CFG);
2814 if (ALC_USECS(sc->alc_int_rx_mod) != 0)
2816 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 &&
2817 ALC_USECS(sc->alc_int_tx_mod) != 0)
2819 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2824 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
2826 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2827 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3);
2828 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER,
2829 ALC_USECS(sc->alc_int_tx_mod));
2831 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) {
2832 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
2833 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
2835 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
2843 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
2845 alc_stats_clear(sc);
2861 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen);
2863 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
2865 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
2867 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
2877 CSR_WRITE_4(sc, ALC_HDPX_CFG,
2893 reg = (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) &
2895 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0)
2897 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);
2899 reg = (alc_dma_burst[sc->alc_dma_rd_burst] <<
2901 if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 ||
2902 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
2907 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
2908 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2913 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);
2919 CSR_WRITE_4(sc, ALC_WRR, reg);
2922 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
2934 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2935 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
2943 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
2949 } else if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C||
2950 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) {
2951 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
2954 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
2961 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
2963 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
2964 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
2971 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
2975 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0)
2978 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 &&
2979 sc->sc_product != PCI_PRODUCT_ATTANSIC_L1D_1)
2982 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
2986 reg |= sc->alc_rcb;
2987 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0)
2989 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0)
2993 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) <<
2995 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) <<
3001 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
3002 switch (AR816X_REV(sc->alc_rev)) {
3014 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3032 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 ||
3033 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D ||
3034 sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 ||
3035 sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2)
3037 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0)
3041 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3044 alc_iff(sc);
3046 alc_rxvlan(sc);
3049 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
3050 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3051 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
3056 sc->alc_flags &= ~ALC_FLAG_LINK;
3060 timeout_add_sec(&sc->alc_tick_ch, 1);
3066 alc_stop(struct alc_softc *sc)
3068 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
3081 timeout_del(&sc->alc_tick_ch);
3082 sc->alc_flags &= ~ALC_FLAG_LINK;
3084 alc_stats_update(sc);
3087 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
3088 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3091 reg = CSR_READ_4(sc, ALC_DMA_CFG);
3094 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3098 alc_stop_mac(sc);
3101 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3104 reg = CSR_READ_4(sc, ALC_PM_CFG);
3107 CSR_WRITE_4(sc, ALC_PM_CFG, reg);
3111 m_freem(sc->alc_cdata.alc_rxhead);
3112 ALC_RXCHAIN_RESET(sc);
3117 rxd = &sc->alc_cdata.alc_rxdesc[i];
3119 bus_dmamap_sync(sc->sc_dmat, rxd->rx_dmamap, 0,
3121 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap);
3127 txd = &sc->alc_cdata.alc_txdesc[i];
3129 bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0,
3131 bus_dmamap_unload(sc->sc_dmat, txd->tx_dmamap);
3139 alc_stop_mac(struct alc_softc *sc)
3144 alc_stop_queue(sc);
3146 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3149 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3152 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3159 sc->sc_dev.dv_xname, reg);
3163 alc_start_queue(struct alc_softc *sc)
3175 cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
3176 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
3182 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
3184 cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
3186 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
3190 alc_stop_queue(struct alc_softc *sc)
3196 reg = CSR_READ_4(sc, ALC_RXQ_CFG);
3197 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
3200 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3205 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3209 reg = CSR_READ_4(sc, ALC_TXQ_CFG);
3212 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
3216 reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3223 sc->sc_dev.dv_xname, reg);
3227 alc_init_tx_ring(struct alc_softc *sc)
3233 sc->alc_cdata.alc_tx_prod = 0;
3234 sc->alc_cdata.alc_tx_cons = 0;
3235 sc->alc_cdata.alc_tx_cnt = 0;
3237 rd = &sc->alc_rdata;
3240 txd = &sc->alc_cdata.alc_txdesc[i];
3244 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0,
3245 sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
3249 alc_init_rx_ring(struct alc_softc *sc)
3255 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1;
3256 rd = &sc->alc_rdata;
3259 rxd = &sc->alc_cdata.alc_rxdesc[i];
3262 if (alc_newbuf(sc, rxd) != 0)
3271 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map, 0,
3272 sc->alc_cdata.alc_rx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
3274 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
3280 alc_init_rr_ring(struct alc_softc *sc)
3284 sc->alc_cdata.alc_rr_cons = 0;
3285 ALC_RXCHAIN_RESET(sc);
3287 rd = &sc->alc_rdata;
3289 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map, 0,
3290 sc->alc_cdata.alc_rr_ring_map->dm_mapsize,
3295 alc_init_cmb(struct alc_softc *sc)
3299 rd = &sc->alc_rdata;
3301 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0,
3302 sc->alc_cdata.alc_cmb_map->dm_mapsize,
3307 alc_init_smb(struct alc_softc *sc)
3311 rd = &sc->alc_rdata;
3313 bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0,
3314 sc->alc_cdata.alc_smb_map->dm_mapsize,
3319 alc_rxvlan(struct alc_softc *sc)
3321 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
3324 reg = CSR_READ_4(sc, ALC_MAC_CFG);
3329 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3333 alc_iff(struct alc_softc *sc)
3335 struct arpcom *ac = &sc->sc_arpcom;
3343 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
3373 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
3374 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
3375 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);