Lines Matching defs:tmp
789 u32 tmp = RREG32(CG_CLKPIN_CNTL);
791 if (tmp & MUX_TCLK_TO_XCLK)
794 if (tmp & XTALIN_DIVIDE)
804 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
808 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
809 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
839 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
840 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
896 u32 tmp;
913 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
917 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
918 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
919 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
921 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
922 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
923 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
924 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
925 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
946 u32 tmp;
959 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
960 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
961 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
962 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
963 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
964 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
965 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
966 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
980 u32 tmp;
990 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
994 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
995 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
996 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
997 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
998 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
999 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1000 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1008 u32 tmp;
1022 tmp = RREG32(HDP_DEBUG1);
1052 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1053 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1054 WREG32(MC_VM_FB_LOCATION, tmp);
1137 u32 tmp, i;
1142 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
1143 tmp &= SCLK_MUX_SEL_MASK;
1144 tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
1145 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1153 tmp &= ~SCLK_MUX_UPDATE;
1154 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1156 tmp = RREG32(MPLL_CNTL_MODE);
1158 tmp &= ~RV730_MPLL_MCLK_SEL;
1160 tmp &= ~MPLL_MCLK_SEL;
1161 WREG32(MPLL_CNTL_MODE, tmp);
1185 u32 db_debug4, tmp;
1304 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
1305 if (!(inactive_pipes & tmp)) {
1308 tmp <<= 1;
1317 tmp = rdev->config.rv770.max_simds -
1319 rdev->config.rv770.active_simds = tmp;
1339 tmp = 0;
1341 tmp |= (1 << i);
1343 if ((disabled_rb_mask & tmp) == tmp) {
1347 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1348 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
1350 gb_tiling_config |= tmp << 16;
1351 rdev->config.rv770.backend_map = tmp;
1644 u32 tmp;
1649 tmp = RREG32(MC_ARB_RAMCFG);
1650 if (tmp & CHANSIZE_OVERRIDE) {
1652 } else if (tmp & CHANSIZE_MASK) {
1657 tmp = RREG32(MC_SHARED_CHMAP);
1658 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2022 u32 link_width_cntl, lanes, speed_cntl, tmp;
2067 tmp = RREG32(0x541c);
2068 WREG32(0x541c, tmp | 0x8);