Lines Matching defs:tmp
124 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
128 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
129 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
152 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
153 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
172 u32 tmp = 0;
192 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
194 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
199 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
202 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
213 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
216 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
219 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
222 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
234 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
239 tmp = RREG32(voltage->gpio.reg);
241 tmp |= voltage->gpio.mask;
243 tmp &= ~(voltage->gpio.mask);
244 WREG32(voltage->gpio.reg, tmp);
248 tmp = RREG32(voltage->gpio.reg);
250 tmp &= ~voltage->gpio.mask;
252 tmp |= voltage->gpio.mask;
253 WREG32(voltage->gpio.reg, tmp);
328 u32 tmp;
334 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
335 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
336 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
346 u32 tmp;
352 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
353 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
354 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
362 u32 tmp;
367 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
368 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
372 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
373 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
385 u32 tmp;
390 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
392 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
394 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
395 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
398 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
400 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
402 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
403 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
466 u32 status, tmp;
479 tmp = RREG32(RADEON_CP_RB_CNTL);
480 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
483 WREG32(RADEON_CP_RB_CNTL, tmp);
530 uint32_t tmp;
532 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
533 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
534 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
536 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
537 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
538 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
540 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
541 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
542 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
543 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
565 u32 tmp;
576 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
577 WREG32(RADEON_BUS_CNTL, tmp);
615 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
616 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
617 tmp = RREG32_MC(R_000009_MC_CNTL1);
618 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
629 u32 tmp;
633 tmp = RREG32_MC(R_000009_MC_CNTL1);
634 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
669 uint32_t tmp = 0;
688 tmp |= S_000040_SW_INT_EN(1);
707 WREG32(R_000040_GEN_INT_CNTL, tmp);
724 u32 tmp;
737 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
738 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
739 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
742 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
743 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
744 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
754 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
755 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
756 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);