Lines Matching defs:seq
62 * @seq: sequence number to write
67 static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
72 *drv->cpu_addr = cpu_to_le32(seq);
75 WREG32(drv->scratch_reg, seq);
91 u32 seq = 0;
95 seq = le32_to_cpu(*drv->cpu_addr);
97 seq = lower_32_bits(atomic64_read(&drv->last_seq));
100 seq = RREG32(drv->scratch_reg);
102 return seq;
138 u64 seq;
146 (*fence)->seq = seq = ++rdev->fence_drv[ring].sync_seq[ring];
152 seq);
154 trace_radeon_fence_emit(rdev_to_drm(rdev), ring, (*fence)->seq);
169 u64 seq;
177 seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq);
178 if (seq >= fence->seq) {
199 uint64_t seq, last_seq, last_emitted;
214 * value the other process set as last seq must be higher than
215 * the seq value we just read. Which means that current process
222 * seq but to an older one.
227 seq = radeon_fence_read(rdev, ring);
228 seq |= last_seq & 0xffffffff00000000LL;
229 if (seq < last_seq) {
230 seq &= 0xffffffff;
231 seq |= last_emitted & 0xffffffff00000000LL;
234 if (seq <= last_seq || seq > last_emitted) {
239 * seq we just read is different from the previous on.
242 last_seq = seq;
246 * seq then the current real last seq as signaled
251 } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
253 if (seq < last_emitted)
330 * @seq: sequence number
341 u64 seq, unsigned ring)
343 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
348 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
359 u64 seq = fence->seq;
361 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
369 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
389 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq)
399 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq) {
434 if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
445 * @seq: sequence numbers
452 static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
457 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i))
538 uint64_t seq[RADEON_NUM_RINGS] = {};
550 seq[fence->ring] = fence->seq;
551 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout);
598 uint64_t seq[RADEON_NUM_RINGS];
603 seq[i] = 0;
609 seq[i] = fences[i]->seq;
617 r = radeon_fence_wait_seq_timeout(rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);
636 uint64_t seq[RADEON_NUM_RINGS] = {};
639 seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
640 if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {
645 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
663 uint64_t seq[RADEON_NUM_RINGS] = {};
666 seq[ring] = rdev->fence_drv[ring].sync_seq[ring];
667 if (!seq[ring])
670 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
764 if (fence->seq <= fdrv->sync_seq[fence->ring]) {