Lines Matching defs:state_index

2651 	int state_index = 0;
2748 			rdev->pm.power_state[state_index].num_clock_modes = 1;
2749 			rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2750 			rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2751 			if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2752 			    (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2754 			rdev->pm.power_state[state_index].type =
2759 			rdev->pm.power_state[state_index].misc = misc;
2760 			rdev->pm.power_state[state_index].misc2 = misc2;
2762 				rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2764 					rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2767 					rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2769 				rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2771 					rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2774 					rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2779 						rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2782 						rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2784 						rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2789 					rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2792 					rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2795 					rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2798 					rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2801 					rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2805 				rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2807 				rdev->pm.power_state[state_index].pcie_lanes =
2809 			rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2810 			state_index++;
2820 	rdev->pm.power_state[state_index].type =
2822 	rdev->pm.power_state[state_index].num_clock_modes = 1;
2823 	rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2824 	rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2825 	rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2826 	if ((state_index > 0) &&
2828 		rdev->pm.power_state[state_index].clock_info[0].voltage =
2831 		rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2832 	rdev->pm.power_state[state_index].pcie_lanes = 16;
2833 	rdev->pm.power_state[state_index].flags = 0;
2834 	rdev->pm.default_power_state_index = state_index;
2835 	rdev->pm.num_power_states = state_index + 1;
2842 	rdev->pm.default_power_state_index = state_index;