Lines Matching defs:bios_5_scratch

3480 	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3489 			bios_5_scratch |= RADEON_TV1_ON;
3490 			bios_5_scratch |= RADEON_ACC_REQ_TV1;
3494 			bios_5_scratch &= ~RADEON_TV1_ON;
3495 			bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3503 			bios_5_scratch |= RADEON_LCD1_ON;
3504 			bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3508 			bios_5_scratch &= ~RADEON_LCD1_ON;
3509 			bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3517 			bios_5_scratch |= RADEON_CRT1_ON;
3518 			bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3522 			bios_5_scratch &= ~RADEON_CRT1_ON;
3523 			bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3531 			bios_5_scratch |= RADEON_CRT2_ON;
3532 			bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3536 			bios_5_scratch &= ~RADEON_CRT2_ON;
3537 			bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3545 			bios_5_scratch |= RADEON_DFP1_ON;
3546 			bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3550 			bios_5_scratch &= ~RADEON_DFP1_ON;
3551 			bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3559 			bios_5_scratch |= RADEON_DFP2_ON;
3560 			bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3564 			bios_5_scratch &= ~RADEON_DFP2_ON;
3565 			bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3569 	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3578 	uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3581 		bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3582 		bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3585 		bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3586 		bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3589 		bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3590 		bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3593 		bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3594 		bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3597 		bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3598 		bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3601 		bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3602 		bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3604 	WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);