Lines Matching defs:state_index
2050 int state_index,
2053 rdev->pm.power_state[state_index].misc = misc;
2054 rdev->pm.power_state[state_index].misc2 = misc2;
2057 rdev->pm.power_state[state_index].type =
2060 rdev->pm.power_state[state_index].type =
2063 rdev->pm.power_state[state_index].type =
2066 rdev->pm.power_state[state_index].type =
2069 rdev->pm.power_state[state_index].type =
2071 rdev->pm.power_state[state_index].flags &=
2075 rdev->pm.power_state[state_index].type =
2078 rdev->pm.power_state[state_index].type =
2080 rdev->pm.default_power_state_index = state_index;
2081 rdev->pm.power_state[state_index].default_clock_mode =
2082 &rdev->pm.power_state[state_index].clock_info[0];
2083 } else if (state_index == 0) {
2084 rdev->pm.power_state[state_index].clock_info[0].flags |=
2094 int state_index = 0;
2103 return state_index;
2129 return state_index;
2134 return state_index;
2138 if (!rdev->pm.power_state[state_index].clock_info) {
2139 rdev->pm.power_state[state_index].clock_info =
2143 if (!rdev->pm.power_state[state_index].clock_info)
2145 rdev->pm.power_state[state_index].num_clock_modes = 1;
2146 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2149 rdev->pm.power_state[state_index].clock_info[0].mclk =
2151 rdev->pm.power_state[state_index].clock_info[0].sclk =
2154 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2155 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2157 rdev->pm.power_state[state_index].pcie_lanes =
2162 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2164 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2168 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2171 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2174 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2176 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2179 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2180 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2181 state_index++;
2184 rdev->pm.power_state[state_index].clock_info[0].mclk =
2186 rdev->pm.power_state[state_index].clock_info[0].sclk =
2189 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2190 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2192 rdev->pm.power_state[state_index].pcie_lanes =
2198 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2200 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2204 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2207 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2210 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2212 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2215 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2216 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2217 state_index++;
2220 rdev->pm.power_state[state_index].clock_info[0].mclk =
2222 rdev->pm.power_state[state_index].clock_info[0].sclk =
2225 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2226 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2228 rdev->pm.power_state[state_index].pcie_lanes =
2234 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2236 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2240 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2243 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2246 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2248 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2251 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2253 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2257 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2258 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2259 state_index++;
2265 if (state_index && state_index < num_modes) {
2266 kfree(rdev->pm.power_state[state_index].clock_info);
2267 rdev->pm.power_state[state_index].clock_info = NULL;
2271 if (state_index && rdev->pm.default_power_state_index == -1) {
2272 rdev->pm.power_state[state_index - 1].type =
2274 rdev->pm.default_power_state_index = state_index - 1;
2275 rdev->pm.power_state[state_index - 1].default_clock_mode =
2276 &rdev->pm.power_state[state_index - 1].clock_info[0];
2277 rdev->pm.power_state[state_index - 1].flags &=
2279 rdev->pm.power_state[state_index - 1].misc = 0;
2280 rdev->pm.power_state[state_index - 1].misc2 = 0;
2282 return state_index;
2413 int state_index, int mode_index,
2423 rdev->pm.power_state[state_index].misc = misc;
2424 rdev->pm.power_state[state_index].misc2 = misc2;
2425 rdev->pm.power_state[state_index].pcie_lanes =
2430 rdev->pm.power_state[state_index].type =
2434 rdev->pm.power_state[state_index].type =
2438 rdev->pm.power_state[state_index].type =
2443 rdev->pm.power_state[state_index].type =
2447 rdev->pm.power_state[state_index].flags = 0;
2449 rdev->pm.power_state[state_index].flags |=
2452 rdev->pm.power_state[state_index].type =
2454 rdev->pm.default_power_state_index = state_index;
2455 rdev->pm.power_state[state_index].default_clock_mode =
2456 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2459 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2460 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2461 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2462 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2472 rdev->pm.power_state[state_index].clock_info[j].mclk =
2474 rdev->pm.power_state[state_index].clock_info[j].sclk =
2477 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2480 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2488 int state_index, int mode_index,
2498 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2502 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2509 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2510 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2511 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2518 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2519 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2520 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2522 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2524 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2531 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2532 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2533 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2535 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2537 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2544 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2545 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2546 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2548 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2553 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2563 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2565 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2573 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2577 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2578 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2590 int state_index = 0, mode_index = 0;
2600 return state_index;
2605 return state_index;
2610 return state_index;
2629 return state_index;
2638 state_index, mode_index,
2644 rdev->pm.power_state[state_index].clock_info[0].mclk =
2646 rdev->pm.power_state[state_index].clock_info[0].sclk =
2650 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2652 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2654 state_index++;
2658 for (i = 0; i < state_index; i++) {
2671 return state_index;
2680 int state_index = 0, mode_index = 0;
2694 return state_index;
2708 return state_index;
2713 return state_index;
2727 return state_index;
2734 state_index, mode_index,
2740 rdev->pm.power_state[state_index].clock_info[0].mclk =
2742 rdev->pm.power_state[state_index].clock_info[0].sclk =
2746 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2748 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2750 state_index++;
2755 for (i = 0; i < state_index; i++) {
2768 return state_index;
2777 int state_index = 0;
2787 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2791 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2794 state_index = radeon_atombios_parse_power_table_6(rdev);
2801 if (state_index == 0) {
2810 rdev->pm.power_state[state_index].type =
2812 rdev->pm.power_state[state_index].num_clock_modes = 1;
2813 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2814 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2815 rdev->pm.power_state[state_index].default_clock_mode =
2816 &rdev->pm.power_state[state_index].clock_info[0];
2817 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2818 rdev->pm.power_state[state_index].pcie_lanes = 16;
2819 rdev->pm.default_power_state_index = state_index;
2820 rdev->pm.power_state[state_index].flags = 0;
2821 state_index++;
2826 rdev->pm.num_power_states = state_index;