Lines Matching defs:tmp

88 	uint32_t tmp;
93 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
94 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
96 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
153 uint32_t tmp;
164 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
165 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
167 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
168 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
178 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
179 tmp |= RADEON_PCIE_TX_GART_EN;
180 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
181 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
192 u32 tmp;
198 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
199 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
200 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
348 uint32_t tmp;
352 tmp = RREG32(RADEON_MC_STATUS);
353 if (tmp & R300_MC_IDLE) {
363 uint32_t gb_tile_config, tmp;
396 tmp = RREG32(R300_DST_PIPE_CONFIG);
397 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
416 u32 status, tmp;
428 tmp = RREG32(RADEON_CP_RB_CNTL);
429 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
432 WREG32(RADEON_CP_RB_CNTL, tmp);
476 u32 tmp;
480 tmp = RREG32(RADEON_MEM_CNTL);
481 tmp &= R300_MEM_NUM_CHANNELS_MASK;
482 switch (tmp) {
593 uint32_t tmp;
595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
596 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
598 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
600 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
601 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
602 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
603 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
604 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
605 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
606 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
607 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
608 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
632 uint32_t tmp, tile_flags = 0;
724 tmp = idx_value + ((u32)reloc->gpu_offset);
725 tmp |= tile_flags;
726 ib[idx] = tmp;
793 tmp = idx_value & ~(0x7 << 16);
794 tmp |= tile_flags;
795 ib[idx] = tmp;
878 tmp = idx_value & ~(0x7 << 16);
879 tmp |= tile_flags;
880 ib[idx] = tmp;
913 tmp = (idx_value >> 25) & 0x3;
914 track->textures[i].tex_coord_type = tmp;
999 tmp = idx_value & 0x7;
1000 if (tmp == 2 || tmp == 4 || tmp == 6) {
1003 tmp = (idx_value >> 3) & 0x7;
1004 if (tmp == 2 || tmp == 4 || tmp == 6) {
1027 tmp = idx_value & 0x3FFF;
1028 track->textures[i].pitch = tmp + 1;
1030 tmp = ((idx_value >> 15) & 1) << 11;
1031 track->textures[i].width_11 = tmp;
1032 tmp = ((idx_value >> 16) & 1) << 11;
1033 track->textures[i].height_11 = tmp;
1065 tmp = idx_value & 0x7FF;
1066 track->textures[i].width = tmp + 1;
1067 tmp = (idx_value >> 11) & 0x7FF;
1068 track->textures[i].height = tmp + 1;
1069 tmp = (idx_value >> 26) & 0xF;
1070 track->textures[i].num_levels = tmp;
1071 tmp = idx_value & (1 << 31);
1072 track->textures[i].use_pitch = !!tmp;
1073 tmp = (idx_value >> 22) & 0xF;
1074 track->textures[i].txdepth = tmp;
1357 u32 tmp;
1362 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1363 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1365 tmp |= S_00000D_FORCE_VAP(1);
1366 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);