Lines Matching defs:src_reloc

2799 	struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;
2854 			r = r600_dma_cs_next_reloc(p, &src_reloc);
2872 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2874 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2883 				ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2885 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2895 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
2905 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2906 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2912 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2914 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2931 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {
2933 							src_offset + count, radeon_bo_size(src_reloc->robj));
2942 				ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff);
2944 				ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2954 				ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff);
2955 				ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
2975 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2977 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2992 				ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
2995 				ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
3015 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3017 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3032 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
3033 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
3046 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
3052 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
3053 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
3077 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3079 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3094 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
3095 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
3106 					ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
3116 					ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
3117 					ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff;
3123 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3125 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3142 				ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);
3164 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3166 							src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3181 				ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc);
3182 				ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff;