Lines Matching refs:val
142 u32 val; in chv_detect_mem_freq() local
145 val = vlv_cck_read(i915, CCK_FUSE_REG); in chv_detect_mem_freq()
148 switch ((val >> 2) & 0x7) { in chv_detect_mem_freq()
160 u32 val; in vlv_detect_mem_freq() local
163 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_detect_mem_freq()
166 switch ((val >> 6) & 3) { in vlv_detect_mem_freq()
201 static int skl_get_dimm_size(u16 val) in skl_get_dimm_size() argument
203 return (val & SKL_DRAM_SIZE_MASK) * 8; in skl_get_dimm_size()
206 static int skl_get_dimm_width(u16 val) in skl_get_dimm_width() argument
208 if (skl_get_dimm_size(val) == 0) in skl_get_dimm_width()
211 switch (val & SKL_DRAM_WIDTH_MASK) { in skl_get_dimm_width()
215 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT; in skl_get_dimm_width()
216 return 8 << val; in skl_get_dimm_width()
218 MISSING_CASE(val); in skl_get_dimm_width()
223 static int skl_get_dimm_ranks(u16 val) in skl_get_dimm_ranks() argument
225 if (skl_get_dimm_size(val) == 0) in skl_get_dimm_ranks()
228 val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT; in skl_get_dimm_ranks()
230 return val + 1; in skl_get_dimm_ranks()
234 static int icl_get_dimm_size(u16 val) in icl_get_dimm_size() argument
236 return (val & ICL_DRAM_SIZE_MASK) * 8 / 2; in icl_get_dimm_size()
239 static int icl_get_dimm_width(u16 val) in icl_get_dimm_width() argument
241 if (icl_get_dimm_size(val) == 0) in icl_get_dimm_width()
244 switch (val & ICL_DRAM_WIDTH_MASK) { in icl_get_dimm_width()
248 val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT; in icl_get_dimm_width()
249 return 8 << val; in icl_get_dimm_width()
251 MISSING_CASE(val); in icl_get_dimm_width()
256 static int icl_get_dimm_ranks(u16 val) in icl_get_dimm_ranks() argument
258 if (icl_get_dimm_size(val) == 0) in icl_get_dimm_ranks()
261 val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT; in icl_get_dimm_ranks()
263 return val + 1; in icl_get_dimm_ranks()
276 int channel, char dimm_name, u16 val) in skl_dram_get_dimm_info() argument
279 dimm->size = icl_get_dimm_size(val); in skl_dram_get_dimm_info()
280 dimm->width = icl_get_dimm_width(val); in skl_dram_get_dimm_info()
281 dimm->ranks = icl_get_dimm_ranks(val); in skl_dram_get_dimm_info()
283 dimm->size = skl_get_dimm_size(val); in skl_dram_get_dimm_info()
284 dimm->width = skl_get_dimm_width(val); in skl_dram_get_dimm_info()
285 dimm->ranks = skl_get_dimm_ranks(val); in skl_dram_get_dimm_info()
297 int channel, u32 val) in skl_dram_get_channel_info() argument
300 channel, 'L', val & 0xffff); in skl_dram_get_channel_info()
302 channel, 'S', val >> 16); in skl_dram_get_channel_info()
339 u32 val; in skl_dram_get_channels_info() local
342 val = intel_uncore_read(&i915->uncore, in skl_dram_get_channels_info()
344 ret = skl_dram_get_channel_info(i915, &ch0, 0, val); in skl_dram_get_channels_info()
348 val = intel_uncore_read(&i915->uncore, in skl_dram_get_channels_info()
350 ret = skl_dram_get_channel_info(i915, &ch1, 1, val); in skl_dram_get_channels_info()
377 u32 val; in skl_get_dram_type() local
379 val = intel_uncore_read(&i915->uncore, in skl_get_dram_type()
382 switch (val & SKL_DRAM_DDR_TYPE_MASK) { in skl_get_dram_type()
392 MISSING_CASE(val); in skl_get_dram_type()
415 static int bxt_get_dimm_size(u32 val) in bxt_get_dimm_size() argument
417 switch (val & BXT_DRAM_SIZE_MASK) { in bxt_get_dimm_size()
429 MISSING_CASE(val); in bxt_get_dimm_size()
434 static int bxt_get_dimm_width(u32 val) in bxt_get_dimm_width() argument
436 if (!bxt_get_dimm_size(val)) in bxt_get_dimm_width()
439 val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT; in bxt_get_dimm_width()
441 return 8 << val; in bxt_get_dimm_width()
444 static int bxt_get_dimm_ranks(u32 val) in bxt_get_dimm_ranks() argument
446 if (!bxt_get_dimm_size(val)) in bxt_get_dimm_ranks()
449 switch (val & BXT_DRAM_RANK_MASK) { in bxt_get_dimm_ranks()
455 MISSING_CASE(val); in bxt_get_dimm_ranks()
460 static enum intel_dram_type bxt_get_dimm_type(u32 val) in bxt_get_dimm_type() argument
462 if (!bxt_get_dimm_size(val)) in bxt_get_dimm_type()
465 switch (val & BXT_DRAM_TYPE_MASK) { in bxt_get_dimm_type()
475 MISSING_CASE(val); in bxt_get_dimm_type()
480 static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val) in bxt_get_dimm_info() argument
482 dimm->width = bxt_get_dimm_width(val); in bxt_get_dimm_info()
483 dimm->ranks = bxt_get_dimm_ranks(val); in bxt_get_dimm_info()
489 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm); in bxt_get_dimm_info()
495 u32 val; in bxt_get_dram_info() local
506 val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i)); in bxt_get_dram_info()
507 if (val == 0xFFFFFFFF) in bxt_get_dram_info()
512 bxt_get_dimm_info(&dimm, val); in bxt_get_dram_info()
513 type = bxt_get_dimm_type(val); in bxt_get_dram_info()
543 u32 val = 0; in icl_pcode_read_mem_global_info() local
547 ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL); in icl_pcode_read_mem_global_info()
552 switch (val & 0xf) { in icl_pcode_read_mem_global_info()
572 MISSING_CASE(val & 0xf); in icl_pcode_read_mem_global_info()
576 switch (val & 0xf) { in icl_pcode_read_mem_global_info()
590 MISSING_CASE(val & 0xf); in icl_pcode_read_mem_global_info()
595 dram_info->num_channels = (val & 0xf0) >> 4; in icl_pcode_read_mem_global_info()
596 dram_info->num_qgv_points = (val & 0xf00) >> 8; in icl_pcode_read_mem_global_info()
597 dram_info->num_psf_gv_points = (val & 0x3000) >> 12; in icl_pcode_read_mem_global_info()
621 u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); in xelpdp_get_dram_info() local
624 switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) { in xelpdp_get_dram_info()
644 MISSING_CASE(val); in xelpdp_get_dram_info()
648 dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val); in xelpdp_get_dram_info()
649 dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val); in xelpdp_get_dram_info()