Lines Matching defs:huc
82 static void __delayed_huc_load_complete(struct intel_huc *huc)
84 if (!i915_sw_fence_done(&huc->delayed_load.fence))
85 i915_sw_fence_complete(&huc->delayed_load.fence);
88 static void delayed_huc_load_complete(struct intel_huc *huc)
90 hrtimer_cancel(&huc->delayed_load.timer);
91 __delayed_huc_load_complete(huc);
94 static void __gsc_init_error(struct intel_huc *huc)
96 huc->delayed_load.status = INTEL_HUC_DELAYED_LOAD_ERROR;
97 __delayed_huc_load_complete(huc);
100 static void gsc_init_error(struct intel_huc *huc)
102 hrtimer_cancel(&huc->delayed_load.timer);
103 __gsc_init_error(huc);
106 static void gsc_init_done(struct intel_huc *huc)
108 hrtimer_cancel(&huc->delayed_load.timer);
111 huc->delayed_load.status = INTEL_HUC_WAITING_ON_PXP;
112 if (!i915_sw_fence_done(&huc->delayed_load.fence))
114 hrtimer_start(&huc->delayed_load.timer,
118 timeout_add_msec(&huc->delayed_load.timer, PXP_INIT_TIMEOUT_MS);
124 struct intel_huc *huc = arg;
126 if (!intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC)) {
127 if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_GSC)
128 huc_notice(huc, "timed out waiting for MEI GSC\n");
129 else if (huc->delayed_load.status == INTEL_HUC_WAITING_ON_PXP)
130 huc_notice(huc, "timed out waiting for MEI PXP\n");
132 MISSING_CASE(huc->delayed_load.status);
134 __gsc_init_error(huc);
138 static void huc_delayed_load_start(struct intel_huc *huc)
142 GEM_BUG_ON(intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC));
148 switch (huc->delayed_load.status) {
156 gsc_init_error(huc);
166 GEM_BUG_ON(!i915_sw_fence_done(&huc->delayed_load.fence));
167 i915_sw_fence_fini(&huc->delayed_load.fence);
168 i915_sw_fence_reinit(&huc->delayed_load.fence);
169 i915_sw_fence_await(&huc->delayed_load.fence);
170 i915_sw_fence_commit(&huc->delayed_load.fence);
173 hrtimer_start(&huc->delayed_load.timer, delay, HRTIMER_MODE_REL);
175 timeout_add_nsec(&huc->delayed_load.timer, ktime_to_ns(delay));
185 struct intel_huc *huc = container_of(nb, struct intel_huc, delayed_load.nb);
186 struct intel_gsc_intf *intf = &huc_to_gt(huc)->gsc.intf[0];
193 gsc_init_done(huc);
198 huc_info(huc, "MEI driver not bound, disabling load\n");
199 gsc_init_error(huc);
207 void intel_huc_register_gsc_notifier(struct intel_huc *huc, const struct bus_type *bus)
211 if (!intel_huc_is_loaded_by_gsc(huc))
214 huc->delayed_load.nb.notifier_call = gsc_notifier;
215 ret = bus_register_notifier(bus, &huc->delayed_load.nb);
217 huc_err(huc, "failed to register GSC notifier %pe\n", ERR_PTR(ret));
218 huc->delayed_load.nb.notifier_call = NULL;
219 gsc_init_error(huc);
223 void intel_huc_unregister_gsc_notifier(struct intel_huc *huc, const struct bus_type *bus)
225 if (!huc->delayed_load.nb.notifier_call)
228 delayed_huc_load_complete(huc);
230 bus_unregister_notifier(bus, &huc->delayed_load.nb);
231 huc->delayed_load.nb.notifier_call = NULL;
234 static void delayed_huc_load_init(struct intel_huc *huc)
240 i915_sw_fence_init(&huc->delayed_load.fence,
242 i915_sw_fence_commit(&huc->delayed_load.fence);
245 hrtimer_init(&huc->delayed_load.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
246 huc->delayed_load.timer.function = huc_delayed_load_timer_callback;
248 timeout_set(&huc->delayed_load.timer, huc_delayed_load_timer_callback,
249 huc);
253 static void delayed_huc_load_fini(struct intel_huc *huc)
259 delayed_huc_load_complete(huc);
260 i915_sw_fence_fini(&huc->delayed_load.fence);
263 int intel_huc_sanitize(struct intel_huc *huc)
265 delayed_huc_load_complete(huc);
266 intel_uc_fw_sanitize(&huc->fw);
293 void intel_huc_init_early(struct intel_huc *huc)
295 struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
296 struct intel_gt *gt = huc_to_gt(huc);
298 intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC, true);
307 delayed_huc_load_init(huc);
310 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED);
315 huc->status[INTEL_HUC_AUTH_BY_GUC].reg = GEN11_HUC_KERNEL_LOAD_INFO;
316 huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_LOAD_SUCCESSFUL;
317 huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_LOAD_SUCCESSFUL;
319 huc->status[INTEL_HUC_AUTH_BY_GUC].reg = HUC_STATUS2;
320 huc->status[INTEL_HUC_AUTH_BY_GUC].mask = HUC_FW_VERIFIED;
321 huc->status[INTEL_HUC_AUTH_BY_GUC].value = HUC_FW_VERIFIED;
325 huc->status[INTEL_HUC_AUTH_BY_GSC].reg = GEN11_HUC_KERNEL_LOAD_INFO;
326 huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HUC_LOAD_SUCCESSFUL;
327 huc->status[INTEL_HUC_AUTH_BY_GSC].value = HUC_LOAD_SUCCESSFUL;
329 huc->status[INTEL_HUC_AUTH_BY_GSC].reg = HECI_FWSTS(MTL_GSC_HECI1_BASE, 5);
330 huc->status[INTEL_HUC_AUTH_BY_GSC].mask = HECI1_FWSTS5_HUC_AUTH_DONE;
331 huc->status[INTEL_HUC_AUTH_BY_GSC].value = HECI1_FWSTS5_HUC_AUTH_DONE;
336 static int check_huc_loading_mode(struct intel_huc *huc)
338 struct intel_gt *gt = huc_to_gt(huc);
339 bool gsc_enabled = huc->fw.has_gsc_headers;
346 huc->loaded_via_gsc = intel_uncore_read(gt->uncore, GUC_SHIM_CONTROL2) &
349 if (huc->loaded_via_gsc && !gsc_enabled) {
350 huc_err(huc, "HW requires a GSC-enabled blob, but we found a legacy one\n");
361 if (!huc->loaded_via_gsc && gsc_enabled && !huc->fw.dma_start_offset) {
362 huc_err(huc, "HW in DMA mode, but we have an incompatible GSC-enabled blob\n");
371 if (huc->loaded_via_gsc) {
375 huc_info(huc, "can't load due to missing mei modules\n");
380 huc_info(huc, "can't load due to missing GSCCS\n");
386 huc_dbg(huc, "loaded by GSC = %s\n", str_yes_no(huc->loaded_via_gsc));
391 int intel_huc_init(struct intel_huc *huc)
393 struct intel_gt *gt = huc_to_gt(huc);
396 err = check_huc_loading_mode(huc);
406 huc_info(huc, "Failed to allocate heci pkt\n");
410 huc->heci_pkt = vma;
413 err = intel_uc_fw_init(&huc->fw);
417 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOADABLE);
422 if (huc->heci_pkt)
423 i915_vma_unpin_and_release(&huc->heci_pkt, 0);
425 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
426 huc_info(huc, "initialization failed %pe\n", ERR_PTR(err));
430 void intel_huc_fini(struct intel_huc *huc)
436 delayed_huc_load_fini(huc);
438 if (huc->heci_pkt)
439 i915_vma_unpin_and_release(&huc->heci_pkt, 0);
441 if (intel_uc_fw_is_loadable(&huc->fw))
442 intel_uc_fw_fini(&huc->fw);
445 void intel_huc_suspend(struct intel_huc *huc)
447 if (!intel_uc_fw_is_loadable(&huc->fw))
455 delayed_huc_load_complete(huc);
458 static const char *auth_mode_string(struct intel_huc *huc,
461 bool partial = huc->fw.has_gsc_headers && type == INTEL_HUC_AUTH_BY_GUC;
479 int intel_huc_wait_for_auth_complete(struct intel_huc *huc,
482 struct intel_gt *gt = huc_to_gt(huc);
502 huc->status[type].reg,
503 huc->status[type].mask,
504 huc->status[type].value,
509 huc_dbg(huc, "auth still in progress, count = %d, freq = %dMHz, status = 0x%08X\n",
511 huc->status[type].reg.reg);
518 huc_warn(huc, "excessive auth time: %lldms! [status = 0x%08X, count = %d, ret = %d]\n",
519 delta_ms, huc->status[type].reg.reg, count, ret);
520 huc_warn(huc, "excessive auth time: [freq = %dMHz, before = %dMHz, perf_limit_reasons = 0x%08X]\n",
524 huc_dbg(huc, "auth took %lldms, freq = %dMHz, before = %dMHz, status = 0x%08X, count = %d, ret = %d\n",
526 before_freq, huc->status[type].reg.reg, count, ret);
530 delayed_huc_load_complete(huc);
533 huc_err(huc, "firmware not verified for %s: %pe\n",
534 auth_mode_string(huc, type), ERR_PTR(ret));
535 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
539 intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
540 huc_info(huc, "authenticated for %s\n", auth_mode_string(huc, type));
546 * @huc: intel_huc structure
555 int intel_huc_auth(struct intel_huc *huc, enum intel_huc_authentication_type type)
557 struct intel_gt *gt = huc_to_gt(huc);
561 if (!intel_uc_fw_is_loaded(&huc->fw))
565 if (intel_huc_is_loaded_by_gsc(huc))
568 if (intel_huc_is_authenticated(huc, type))
577 ret = intel_guc_auth_huc(guc, intel_guc_ggtt_offset(guc, huc->fw.rsa_data));
580 ret = intel_huc_fw_auth_via_gsccs(huc);
590 ret = intel_huc_wait_for_auth_complete(huc, type);
597 huc_probe_error(huc, "%s authentication failed %pe\n",
598 auth_mode_string(huc, type), ERR_PTR(ret));
602 bool intel_huc_is_authenticated(struct intel_huc *huc,
605 struct intel_gt *gt = huc_to_gt(huc);
610 status = intel_uncore_read(gt->uncore, huc->status[type].reg);
612 return (status & huc->status[type].mask) == huc->status[type].value;
615 static bool huc_is_fully_authenticated(struct intel_huc *huc)
617 struct intel_uc_fw *huc_fw = &huc->fw;
620 return intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GUC);
621 else if (intel_huc_is_loaded_by_gsc(huc) || HAS_ENGINE(huc_to_gt(huc), GSC0))
622 return intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GSC);
629 * @huc: intel_huc structure
637 int intel_huc_check_status(struct intel_huc *huc)
639 struct intel_uc_fw *huc_fw = &huc->fw;
662 if (huc_is_fully_authenticated(huc))
664 else if (huc_fw->has_gsc_headers && !intel_huc_is_loaded_by_gsc(huc) &&
665 intel_huc_is_authenticated(huc, INTEL_HUC_AUTH_BY_GUC))
671 static bool huc_has_delayed_load(struct intel_huc *huc)
673 return intel_huc_is_loaded_by_gsc(huc) &&
674 (huc->delayed_load.status != INTEL_HUC_DELAYED_LOAD_ERROR);
677 void intel_huc_update_auth_status(struct intel_huc *huc)
679 if (!intel_uc_fw_is_loadable(&huc->fw))
682 if (!huc->fw.has_gsc_headers)
685 if (huc_is_fully_authenticated(huc))
686 intel_uc_fw_change_status(&huc->fw,
688 else if (huc_has_delayed_load(huc))
689 huc_delayed_load_start(huc);
694 * @huc: the HuC
699 void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p)
701 struct intel_gt *gt = huc_to_gt(huc);
704 if (!intel_huc_is_supported(huc)) {
709 if (!intel_huc_is_wanted(huc)) {
714 intel_uc_fw_dump(&huc->fw, p);
718 intel_uncore_read(gt->uncore, huc->status[INTEL_HUC_AUTH_BY_GUC].reg));