Lines Matching defs:ctrl1
1275 pll->state.hw_state.ctrl1 << (id * 6));
1343 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1381 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1705 u32 ctrl1, cfgcr1, cfgcr2;
1712 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1714 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1731 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1744 u32 ctrl1;
1750 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1753 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1756 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1759 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1763 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1766 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1769 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1773 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1784 switch ((pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >>
1861 * ctrl1 register is already shifted for each pll, just use 0 to get
1864 if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
1880 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
1881 hw_state->ctrl1,