Lines Matching defs:dpll
1184 if (i915->display.dpll.mgr) {
2796 struct dpll clock;
2801 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2824 struct dpll clock;
2829 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2982 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
2991 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
3822 u32 dpll = pipe_config->dpll_hw_state.dpll;
3824 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
3840 u32 dpll = pipe_config->dpll_hw_state.dpll;
3842 struct dpll clock;
3846 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3862 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3865 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3868 switch (dpll & DPLL_MODE_MASK) {
3870 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3874 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3880 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3896 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3904 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3907 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3910 if (dpll & PLL_P2_DIVIDE_BY_4)
5313 if (dev_priv->display.dpll.mgr) {
5316 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
7902 struct dpll clock = {
7909 u32 dpll, fp;
7920 dpll = DPLL_DVO_2X_MODE |
7950 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
7951 intel_de_write(dev_priv, DPLL(pipe), dpll);
7962 intel_de_write(dev_priv, DPLL(pipe), dpll);
7966 intel_de_write(dev_priv, DPLL(pipe), dpll);