Lines Matching defs:uint8_t
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
235 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
236 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
245 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
448 uint8_t h_border;
449 uint8_t v_border;
451 uint8_t atom_mode_id;
452 uint8_t refreshrate;
491 uint8_t mem_module_id;
492 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
493 uint8_t reserved1[2];
530 uint8_t mem_module_id;
531 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
532 uint8_t reserved1[2];
535 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
536 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
537 uint8_t board_i2c_feature_slave_addr;
538 uint8_t reserved3;
558 uint8_t mem_module_id;
559 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
560 uint8_t reserved1[2];
563 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
564 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
565 uint8_t board_i2c_feature_slave_addr;
566 uint8_t reserved3;
586 uint8_t mem_module_id;
587 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
588 uint8_t reserved1[2];
591 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
592 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
593 uint8_t board_i2c_feature_slave_addr;
594 uint8_t ras_rom_i2c_slave_addr;
629 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
630 uint8_t pwr_on_de_to_vary_bl;
631 uint8_t pwr_down_vary_bloff_to_de;
632 uint8_t pwr_down_de_to_digoff;
633 uint8_t pwr_off_delay;
634 uint8_t pwr_on_vary_bl_to_blon;
635 uint8_t pwr_down_bloff_to_vary_bloff;
636 uint8_t panel_bpc;
637 uint8_t dpcd_edp_config_cap;
638 uint8_t dpcd_max_link_rate;
639 uint8_t dpcd_max_lane_count;
640 uint8_t dpcd_max_downspread;
641 uint8_t min_allowed_bl_level;
642 uint8_t max_allowed_bl_level;
643 uint8_t bootup_bl_level;
644 uint8_t dplvdsrxid;
671 uint8_t gpio_bitshift;
672 uint8_t gpio_mask_bitshift;
673 uint8_t gpio_id;
674 uint8_t reserved;
793 uint8_t record_type; //An emun to indicate the record type
794 uint8_t record_size; //The size of the whole record in byte
800 uint8_t i2c_id;
801 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
807 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
808 uint8_t plugin_pin_state;
860 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
861 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
867 uint8_t flag; // Future expnadibility
868 uint8_t number_of_pins; // Number of GPIO pins used to control the object
906 uint8_t hpd_pin_map[8];
912 uint8_t aux_ddc_map[8];
919 uint8_t maxtmdsclkrate_in2_5mhz;
920 uint8_t reserved;
926 uint8_t connector_type;
927 uint8_t position;
943 uint8_t bracketlen;
944 uint8_t bracketwidth;
945 uint8_t conn_num;
946 uint8_t reserved;
952 uint8_t bracketlen; //Bracket Length in mm
953 uint8_t bracketwidth; //Bracket Width in mm
954 uint8_t conn_num; //Connector numbering
955 uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini)
956 uint8_t reserved1;
957 uint8_t reserved2;
986 uint8_t priority_id;
987 uint8_t reserved;
1007 uint8_t number_of_path;
1008 uint8_t reserved;
1015 uint8_t number_of_path;
1016 uint8_t reserved;
1040 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1041 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1042 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1043 uint8_t ss_reserved;
1044 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
1045 uint8_t reserved1[3];
1048 uint8_t dceip_min_ver;
1049 uint8_t dceip_max_ver;
1050 uint8_t max_disp_pipe_num;
1051 uint8_t max_vbios_active_disp_pipe_num;
1052 uint8_t max_ppll_num;
1053 uint8_t max_disp_phy_num;
1054 uint8_t max_aux_pairs;
1055 uint8_t remotedisplayconfig;
1056 uint8_t reserved3[8];
1072 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1073 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1074 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1075 uint8_t ss_reserved;
1076 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1077 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1078 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1079 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1082 uint8_t dcnip_min_ver;
1083 uint8_t dcnip_max_ver;
1084 uint8_t max_disp_pipe_num;
1085 uint8_t max_vbios_active_disp_pipe_num;
1086 uint8_t max_ppll_num;
1087 uint8_t max_disp_phy_num;
1088 uint8_t max_aux_pairs;
1089 uint8_t remotedisplayconfig;
1090 uint8_t reserved3[8];
1106 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1107 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1108 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1109 uint8_t ss_reserved;
1110 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1111 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1112 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1113 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1116 uint8_t dcnip_min_ver;
1117 uint8_t dcnip_max_ver;
1118 uint8_t max_disp_pipe_num;
1119 uint8_t max_vbios_active_disp_pipe_num;
1120 uint8_t max_ppll_num;
1121 uint8_t max_disp_phy_num;
1122 uint8_t max_aux_pairs;
1123 uint8_t remotedisplayconfig;
1124 uint8_t reserved3[8];
1139 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1140 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1141 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1142 uint8_t ss_reserved;
1143 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1144 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1145 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1146 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1149 uint8_t dcnip_min_ver;
1150 uint8_t dcnip_max_ver;
1151 uint8_t max_disp_pipe_num;
1152 uint8_t max_vbios_active_disp_pipum;
1153 uint8_t max_ppll_num;
1154 uint8_t max_disp_phy_num;
1155 uint8_t max_aux_pairs;
1156 uint8_t remotedisplayconfig;
1206 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1207 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1208 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1209 uint8_t ss_reserved;
1211 uint8_t dfp_hardcode_mode_num;
1213 uint8_t dfp_hardcode_refreshrate;
1215 uint8_t vga_hardcode_mode_num;
1217 uint8_t vga_hardcode_refreshrate;
1220 uint8_t dcnip_min_ver;
1221 uint8_t dcnip_max_ver;
1222 uint8_t max_disp_pipe_num;
1223 uint8_t max_vbios_active_disp_pipe_num;
1224 uint8_t max_ppll_num;
1225 uint8_t max_disp_phy_num;
1226 uint8_t max_aux_pairs;
1227 uint8_t remotedisplayconfig;
1260 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
1261 uint8_t hpdlut_index; //An index into external HPD pin LUT
1263 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
1264 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
1282 uint8_t guid[16]; // a GUID is a 16 byte long string
1284 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
1285 uint8_t stereopinid; // use for eDP panel
1286 uint8_t remotedisplayconfig;
1287 uint8_t edptolvdsrxid;
1288 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
1289 uint8_t reserved[3]; // for potential expansion
1300 uint8_t profile_id; // SENSOR_PROFILES
1311 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1312 uint8_t module_name[8];
1318 uint8_t flashlight_id; // 0: Rear, 1: Front
1319 uint8_t name[8];
1335 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1336 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1338 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1339 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1340 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1341 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1345 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1347 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1348 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1352 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1353 uint8_t version;
1368 uint8_t sym_clk;
1369 uint8_t dig_mode;
1370 uint8_t phy_sel;
1372 uint8_t common_seldeemph60__deemph_6db_4_val;
1373 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1374 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1375 uint8_t margin_deemph_lane0__deemph_sel_val;
1381 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1382 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1383 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1384 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1385 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1386 uint8_t reserved1;
1387 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1388 uint8_t reserved2;
1392 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1393 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1394 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1395 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1396 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1400 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1401 uint8_t version;
1408 uint8_t ucI2cRegIndex;
1409 uint8_t ucI2cRegVal;
1413 uint8_t HdmiSlvAddr;
1414 uint8_t HdmiRegNum;
1415 uint8_t Hdmi6GRegNum;
1438 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1439 uint8_t umachannelnumber; // number of memory channels
1440 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1441 uint8_t pwr_on_de_to_vary_bl;
1442 uint8_t pwr_down_vary_bloff_to_de;
1443 uint8_t pwr_down_de_to_digoff;
1444 uint8_t pwr_off_delay;
1445 uint8_t pwr_on_vary_bl_to_blon;
1446 uint8_t pwr_down_bloff_to_vary_bloff;
1447 uint8_t min_allowed_bl_level;
1448 uint8_t htc_hyst_limit;
1449 uint8_t htc_tmp_limit;
1450 uint8_t reserved1;
1451 uint8_t reserved2;
1487 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1488 uint8_t umachannelnumber; // number of memory channels
1489 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms //
1490 uint8_t pwr_on_de_to_vary_bl;
1491 uint8_t pwr_down_vary_bloff_to_de;
1492 uint8_t pwr_down_de_to_digoff;
1493 uint8_t pwr_off_delay;
1494 uint8_t pwr_on_vary_bl_to_blon;
1495 uint8_t pwr_down_bloff_to_vary_bloff;
1496 uint8_t min_allowed_bl_level;
1497 uint8_t htc_hyst_limit;
1498 uint8_t htc_tmp_limit;
1499 uint8_t reserved1;
1500 uint8_t reserved2;
1526 uint8_t edp_pwr_on_off_delay;
1527 uint8_t edp_pwr_on_vary_bl_to_blon;
1528 uint8_t edp_pwr_down_bloff_to_vary_bloff;
1529 uint8_t edp_panel_bpc;
1530 uint8_t edp_bootup_bl_level;
1531 uint8_t reserved3[3];
1545 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1546 uint8_t umachannelnumber; // number of memory channels
1547 uint8_t htc_hyst_limit;
1548 uint8_t htc_tmp_limit;
1549 uint8_t reserved1;
1550 uint8_t reserved2;
1576 uint8_t display_signal_type;
1577 uint8_t phy_sel;
1578 uint8_t preset_level;
1579 uint8_t reserved1;
1582 uint8_t tx_vboost_level;
1583 uint8_t tx_vreg_v2i;
1584 uint8_t tx_vregdrv_byp;
1585 uint8_t tx_term_cntl;
1586 uint8_t tx_peak_level;
1587 uint8_t tx_slew_en;
1588 uint8_t tx_eq_pre;
1589 uint8_t tx_eq_main;
1590 uint8_t tx_eq_post;
1591 uint8_t tx_en_inv_pre;
1592 uint8_t tx_en_inv_post;
1593 uint8_t reserved3;
1614 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1615 uint8_t umachannelnumber; // number of memory channels
1616 uint8_t htc_hyst_limit;
1617 uint8_t htc_tmp_limit;
1618 uint8_t reserved1;
1619 uint8_t reserved2;
1630 uint8_t memoryCarvedGb; //memory carved out with setting
1631 uint8_t memoryRemainingGb; //memory remaining on system
1634 uint8_t Auto : 1;
1635 uint8_t Custom : 1;
1636 uint8_t Reserved : 6;
1638 uint8_t all8;
1651 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1652 uint8_t umachannelnumber; // number of memory channels
1653 uint8_t htc_hyst_limit;
1654 uint8_t htc_tmp_limit;
1655 uint8_t reserved1; // dp_ss_control
1656 uint8_t gpu_package_id;
1661 uint8_t UMACarveoutVersion;
1662 uint8_t UMACarveoutIndexMax;
1663 uint8_t UMACarveoutTypeDefault;
1664 uint8_t UMACarveoutIndexDefault;
1665 uint8_t UMACarveoutType; //Auto or Custom
1666 uint8_t UMACarveoutIndex;
1668 uint8_t reserved3[110];
1754 uint8_t gfxip_min_ver;
1755 uint8_t gfxip_max_ver;
1756 uint8_t max_shader_engines;
1757 uint8_t max_tile_pipes;
1758 uint8_t max_cu_per_sh;
1759 uint8_t max_sh_per_se;
1760 uint8_t max_backends_per_se;
1761 uint8_t max_texture_channel_caches;
1774 uint8_t gfxip_min_ver;
1775 uint8_t gfxip_max_ver;
1776 uint8_t max_shader_engines;
1777 uint8_t max_tile_pipes;
1778 uint8_t max_cu_per_sh;
1779 uint8_t max_sh_per_se;
1780 uint8_t max_backends_per_se;
1781 uint8_t max_texture_channel_caches;
1790 uint8_t active_cu_per_sh;
1791 uint8_t active_rb_per_se;
1799 uint8_t gfxip_min_ver;
1800 uint8_t gfxip_max_ver;
1801 uint8_t max_shader_engines;
1802 uint8_t reserved;
1803 uint8_t max_cu_per_sh;
1804 uint8_t max_sh_per_se;
1805 uint8_t max_backends_per_se;
1806 uint8_t max_texture_channel_caches;
1815 uint8_t active_cu_per_sh;
1816 uint8_t active_rb_per_se;
1824 uint8_t gc_num_max_gs_thds;
1825 uint8_t gc_gs_table_depth;
1826 uint8_t gc_double_offchip_lds_buffer;
1827 uint8_t gc_max_scratch_slots_per_cu;
1834 uint8_t gfxip_min_ver;
1835 uint8_t gfxip_max_ver;
1836 uint8_t max_shader_engines;
1837 uint8_t reserved;
1838 uint8_t max_cu_per_sh;
1839 uint8_t max_sh_per_se;
1840 uint8_t max_backends_per_se;
1841 uint8_t max_texture_channel_caches;
1850 uint8_t active_cu_per_sh;
1851 uint8_t active_rb_per_se;
1859 uint8_t gc_num_max_gs_thds;
1860 uint8_t gc_gs_table_depth;
1861 uint8_t gc_double_offchip_lds_buffer;
1862 uint8_t gc_max_scratch_slots_per_cu;
1865 uint8_t cut_cu;
1866 uint8_t active_cu_total;
1867 uint8_t cu_reserved[2];
1869 uint8_t inactive_cu_per_se[8];
1875 uint8_t gfxip_min_ver;
1876 uint8_t gfxip_max_ver;
1877 uint8_t max_shader_engines;
1878 uint8_t max_tile_pipes;
1879 uint8_t max_cu_per_sh;
1880 uint8_t max_sh_per_se;
1881 uint8_t max_backends_per_se;
1882 uint8_t max_texture_channel_caches;
1891 uint8_t active_wgp_per_se;
1892 uint8_t active_rb_per_se;
1893 uint8_t active_se;
1894 uint8_t reserved1;
1899 uint8_t inactive_wgp[16];
1900 uint8_t inactive_rb[16];
1914 uint8_t smuip_min_ver;
1915 uint8_t smuip_max_ver;
1916 uint8_t smu_rsd1;
1917 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1923 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1924 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1925 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1926 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1927 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1928 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1929 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1930 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1935 uint8_t smuip_min_ver;
1936 uint8_t smuip_max_ver;
1937 uint8_t smu_rsd1;
1938 uint8_t gpuclk_ss_mode;
1944 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1945 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1946 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1947 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1948 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1949 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1950 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1951 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1952 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1953 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
1968 uint8_t smuip_min_ver;
1969 uint8_t smuip_max_ver;
1970 uint8_t waflclk_ss_mode;
1971 uint8_t gpuclk_ss_mode;
1977 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1978 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1979 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1980 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1981 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1982 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1983 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1984 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1985 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1986 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
2009 uint8_t smuip_min_ver;
2010 uint8_t smuip_max_ver;
2011 uint8_t waflclk_ss_mode;
2012 uint8_t gpuclk_ss_mode;
2020 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
2021 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
2066 uint8_t smuip_min_ver;
2067 uint8_t smuip_max_ver;
2068 uint8_t waflclk_ss_mode;
2069 uint8_t gpuclk_ss_mode;
2077 uint8_t pcc_gpio_bit;
2078 uint8_t pcc_gpio_polarity;
2132 uint8_t pcc_gpio_bit;
2133 uint8_t pcc_gpio_polarity;
2195 uint8_t liquid1_i2c_address;
2196 uint8_t liquid2_i2c_address;
2197 uint8_t vr_i2c_address;
2198 uint8_t plx_i2c_address;
2200 uint8_t liquid_i2c_linescl;
2201 uint8_t liquid_i2c_linesda;
2202 uint8_t vr_i2c_linescl;
2203 uint8_t vr_i2c_linesda;
2205 uint8_t plx_i2c_linescl;
2206 uint8_t plx_i2c_linesda;
2207 uint8_t vrsensorpresent;
2208 uint8_t liquidsensorpresent;
2213 uint8_t vddgfxvrmapping;
2214 uint8_t vddsocvrmapping;
2215 uint8_t vddmem0vrmapping;
2216 uint8_t vddmem1vrmapping;
2218 uint8_t gfxulvphasesheddingmask;
2219 uint8_t soculvphasesheddingmask;
2220 uint8_t padding8_v[2];
2223 uint8_t gfxoffset;
2224 uint8_t padding_telemetrygfx;
2227 uint8_t socoffset;
2228 uint8_t padding_telemetrysoc;
2231 uint8_t mem0offset;
2232 uint8_t padding_telemetrymem0;
2235 uint8_t mem1offset;
2236 uint8_t padding_telemetrymem1;
2238 uint8_t acdcgpio;
2239 uint8_t acdcpolarity;
2240 uint8_t vr0hotgpio;
2241 uint8_t vr0hotpolarity;
2243 uint8_t vr1hotgpio;
2244 uint8_t vr1hotpolarity;
2245 uint8_t padding1;
2246 uint8_t padding2;
2248 uint8_t ledpin0;
2249 uint8_t ledpin1;
2250 uint8_t ledpin2;
2251 uint8_t padding8_4;
2253 uint8_t pllgfxclkspreadenabled;
2254 uint8_t pllgfxclkspreadpercent;
2257 uint8_t uclkspreadenabled;
2258 uint8_t uclkspreadpercent;
2261 uint8_t socclkspreadenabled;
2262 uint8_t socclkspreadpercent;
2265 uint8_t acggfxclkspreadenabled;
2266 uint8_t acggfxclkspreadpercent;
2269 uint8_t Vr2_I2C_address;
2270 uint8_t padding_vr2[3];
2283 uint8_t liquid1_i2c_address;
2284 uint8_t liquid2_i2c_address;
2285 uint8_t vr_i2c_address;
2286 uint8_t plx_i2c_address;
2288 uint8_t liquid_i2c_linescl;
2289 uint8_t liquid_i2c_linesda;
2290 uint8_t vr_i2c_linescl;
2291 uint8_t vr_i2c_linesda;
2293 uint8_t plx_i2c_linescl;
2294 uint8_t plx_i2c_linesda;
2295 uint8_t vrsensorpresent;
2296 uint8_t liquidsensorpresent;
2301 uint8_t vddgfxvrmapping;
2302 uint8_t vddsocvrmapping;
2303 uint8_t vddmem0vrmapping;
2304 uint8_t vddmem1vrmapping;
2306 uint8_t gfxulvphasesheddingmask;
2307 uint8_t soculvphasesheddingmask;
2308 uint8_t externalsensorpresent;
2309 uint8_t padding8_v;
2312 uint8_t gfxoffset;
2313 uint8_t padding_telemetrygfx;
2316 uint8_t socoffset;
2317 uint8_t padding_telemetrysoc;
2320 uint8_t mem0offset;
2321 uint8_t padding_telemetrymem0;
2324 uint8_t mem1offset;
2325 uint8_t padding_telemetrymem1;
2327 uint8_t acdcgpio;
2328 uint8_t acdcpolarity;
2329 uint8_t vr0hotgpio;
2330 uint8_t vr0hotpolarity;
2332 uint8_t vr1hotgpio;
2333 uint8_t vr1hotpolarity;
2334 uint8_t padding1;
2335 uint8_t padding2;
2337 uint8_t ledpin0;
2338 uint8_t ledpin1;
2339 uint8_t ledpin2;
2340 uint8_t padding8_4;
2342 uint8_t pllgfxclkspreadenabled;
2343 uint8_t pllgfxclkspreadpercent;
2346 uint8_t uclkspreadenabled;
2347 uint8_t uclkspreadpercent;
2350 uint8_t fclkspreadenabled;
2351 uint8_t fclkspreadpercent;
2354 uint8_t fllgfxclkspreadenabled;
2355 uint8_t fllgfxclkspreadpercent;
2379 uint8_t vddgfxvrmapping;
2380 uint8_t vddsocvrmapping;
2381 uint8_t vddmem0vrmapping;
2382 uint8_t vddmem1vrmapping;
2384 uint8_t gfxulvphasesheddingmask;
2385 uint8_t soculvphasesheddingmask;
2386 uint8_t externalsensorpresent;
2387 uint8_t padding8_v;
2390 uint8_t gfxoffset;
2391 uint8_t padding_telemetrygfx;
2394 uint8_t socoffset;
2395 uint8_t padding_telemetrysoc;
2398 uint8_t mem0offset;
2399 uint8_t padding_telemetrymem0;
2402 uint8_t mem1offset;
2403 uint8_t padding_telemetrymem1;
2406 uint8_t acdcgpio;
2407 uint8_t acdcpolarity;
2408 uint8_t vr0hotgpio;
2409 uint8_t vr0hotpolarity;
2411 uint8_t vr1hotgpio;
2412 uint8_t vr1hotpolarity;
2413 uint8_t padding1;
2414 uint8_t padding2;
2417 uint8_t ledpin0;
2418 uint8_t ledpin1;
2419 uint8_t ledpin2;
2420 uint8_t padding8_4;
2423 uint8_t pllgfxclkspreadenabled;
2424 uint8_t pllgfxclkspreadpercent;
2428 uint8_t uclkspreadenabled;
2429 uint8_t uclkspreadpercent;
2433 uint8_t fclkspreadenabled;
2434 uint8_t fclkspreadpercent;
2438 uint8_t fllgfxclkspreadenabled;
2439 uint8_t fllgfxclkspreadpercent;
2485 uint8_t Enabled;
2486 uint8_t Speed;
2487 uint8_t Padding[2];
2489 uint8_t ControllerPort;
2490 uint8_t ControllerName;
2491 uint8_t ThermalThrotter;
2492 uint8_t I2cProtocol;
2506 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2507 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2508 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2509 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2511 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2512 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2513 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2514 uint8_t Padding8_V;
2518 uint8_t GfxOffset; // in Amps
2519 uint8_t Padding_TelemetryGfx;
2521 uint8_t SocOffset; // in Amps
2522 uint8_t Padding_TelemetrySoc;
2525 uint8_t Mem0Offset; // in Amps
2526 uint8_t Padding_TelemetryMem0;
2529 uint8_t Mem1Offset; // in Amps
2530 uint8_t Padding_TelemetryMem1;
2533 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2534 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2535 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2536 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2538 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2539 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2540 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2541 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2544 uint8_t LedPin0; // GPIO number for LedPin[0]
2545 uint8_t LedPin1; // GPIO number for LedPin[1]
2546 uint8_t LedPin2; // GPIO number for LedPin[2]
2547 uint8_t padding8_4;
2550 uint8_t PllGfxclkSpreadEnabled; // on or off
2551 uint8_t PllGfxclkSpreadPercent; // Q4.4
2555 uint8_t DfllGfxclkSpreadEnabled; // on or off
2556 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2560 uint8_t UclkSpreadEnabled; // on or off
2561 uint8_t UclkSpreadPercent; // Q4.4
2565 uint8_t SoclkSpreadEnabled; // on or off
2566 uint8_t SocclkSpreadPercent; // Q4.4
2589 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
2590 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
2591 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
2592 uint8_t boardvrmapping; // use vr_mapping* bitfields
2594 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
2595 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
2596 uint8_t padding8_v[2];
2600 uint8_t gfxoffset; // in amps
2601 uint8_t padding_telemetrygfx;
2604 uint8_t socoffset; // in amps
2605 uint8_t padding_telemetrysoc;
2608 uint8_t memoffset; // in amps
2609 uint8_t padding_telemetrymem;
2612 uint8_t boardoffset; // in amps
2613 uint8_t padding_telemetryboardinput;
2616 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
2617 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
2618 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
2619 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
2622 uint8_t pllgfxclkspreadenabled; // on or off
2623 uint8_t pllgfxclkspreadpercent; // q4.4
2627 uint8_t uclkspreadenabled; // on or off
2628 uint8_t uclkspreadpercent; // q4.4
2632 uint8_t fclkspreadenabled; // on or off
2633 uint8_t fclkspreadpercent; // q4.4
2638 uint8_t fllgfxclkspreadenabled; // on or off
2639 uint8_t fllgfxclkspreadpercent; // q4.4
2648 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
2649 uint8_t paddingmem[3];
2656 uint8_t xgmilinkspeed[4];
2657 uint8_t xgmilinkwidth[4];
2677 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2678 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2679 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2680 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2682 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2683 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2684 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2685 uint8_t Padding8_V;
2689 uint8_t GfxOffset; // in Amps
2690 uint8_t Padding_TelemetryGfx;
2692 uint8_t SocOffset; // in Amps
2693 uint8_t Padding_TelemetrySoc;
2696 uint8_t Mem0Offset; // in Amps
2697 uint8_t Padding_TelemetryMem0;
2700 uint8_t Mem1Offset; // in Amps
2701 uint8_t Padding_TelemetryMem1;
2704 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2705 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2706 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2707 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2709 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2710 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2711 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2712 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2715 uint8_t LedPin0; // GPIO number for LedPin[0]
2716 uint8_t LedPin1; // GPIO number for LedPin[1]
2717 uint8_t LedPin2; // GPIO number for LedPin[2]
2718 uint8_t padding8_4;
2721 uint8_t PllGfxclkSpreadEnabled; // on or off
2722 uint8_t PllGfxclkSpreadPercent; // Q4.4
2726 uint8_t DfllGfxclkSpreadEnabled; // on or off
2727 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2731 uint8_t UclkSpreadEnabled; // on or off
2732 uint8_t UclkSpreadPercent; // Q4.4
2736 uint8_t SoclkSpreadEnabled; // on or off
2737 uint8_t SocclkSpreadPercent; // Q4.4
2748 uint8_t GpioI2cScl; // Serial Clock
2749 uint8_t GpioI2cSda; // Serial Data
2753 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
2754 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
2758 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT]
2760 uint8_t MvddUlvPhaseSheddingMask;
2761 uint8_t VddciUlvPhaseSheddingMask;
2762 uint8_t Padding8_Psi1;
2763 uint8_t Padding8_Psi2;
2770 uint8_t Enabled;
2771 uint8_t Speed;
2772 uint8_t SlaveAddress;
2773 uint8_t ControllerPort;
2774 uint8_t ControllerName;
2775 uint8_t ThermalThrotter;
2776 uint8_t I2cProtocol;
2777 uint8_t PaddingConfig;
2790 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
2791 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
2792 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
2793 uint8_t I2cSpare;
2796 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2797 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2798 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2799 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2801 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2802 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2803 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2804 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2808 uint8_t GfxOffset; // in Amps
2809 uint8_t Padding_TelemetryGfx;
2812 uint8_t SocOffset; // in Amps
2813 uint8_t Padding_TelemetrySoc;
2816 uint8_t Mem0Offset; // in Amps
2817 uint8_t Padding_TelemetryMem0;
2820 uint8_t Mem1Offset; // in Amps
2821 uint8_t Padding_TelemetryMem1;
2826 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2827 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2828 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2829 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2831 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2832 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2833 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2834 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2837 uint8_t LedPin0; // GPIO number for LedPin[0]
2838 uint8_t LedPin1; // GPIO number for LedPin[1]
2839 uint8_t LedPin2; // GPIO number for LedPin[2]
2840 uint8_t LedEnableMask;
2842 uint8_t LedPcie; // GPIO number for PCIE results
2843 uint8_t LedError; // GPIO number for Error Cases
2844 uint8_t LedSpare1[2];
2849 uint8_t PllGfxclkSpreadEnabled; // on or off
2850 uint8_t PllGfxclkSpreadPercent; // Q4.4
2854 uint8_t DfllGfxclkSpreadEnabled; // on or off
2855 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2859 uint8_t UclkSpreadEnabled; // on or off
2860 uint8_t UclkSpreadPercent; // Q4.4
2864 uint8_t FclkSpreadEnabled; // on or off
2865 uint8_t FclkSpreadPercent; // Q4.4
2871 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
2872 uint8_t PaddingMem1[3];
2879 uint8_t XgmiLinkSpeed [4];
2880 uint8_t XgmiLinkWidth [4];
2898 uint8_t GfxOffset; // in Amps
2899 uint8_t Padding_TelemetryGfx;
2902 uint8_t SocOffset; // in Amps
2903 uint8_t Padding_TelemetrySoc;
2906 uint8_t MemOffset; // in Amps
2907 uint8_t Padding_TelemetryMem;
2910 uint8_t BoardOffset; // in Amps
2911 uint8_t Padding_TelemetryBoardInput;
2918 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2919 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2920 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2921 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2924 uint8_t UclkSpreadEnabled; // on or off
2925 uint8_t UclkSpreadPercent; // Q4.4
2929 uint8_t FclkSpreadEnabled; // on or off
2930 uint8_t FclkSpreadPercent; // Q4.4
2937 uint8_t GpioI2cScl; // Serial Clock
2938 uint8_t GpioI2cSda; // Serial Data
2973 uint8_t enable_gb_vdroop_table_cksoff;
2974 uint8_t enable_gb_vdroop_table_ckson;
2975 uint8_t enable_gb_fuse_table_cksoff;
2976 uint8_t enable_gb_fuse_table_ckson;
2978 uint8_t enable_apply_avfs_cksoff_voltage;
2979 uint8_t reserved;
3017 uint8_t enable_gb_vdroop_table_cksoff;
3018 uint8_t enable_gb_vdroop_table_ckson;
3019 uint8_t enable_gb_fuse_table_cksoff;
3020 uint8_t enable_gb_fuse_table_ckson;
3022 uint8_t enable_apply_avfs_cksoff_voltage;
3023 uint8_t reserved;
3042 uint8_t enable_acg_gb_vdroop_table;
3043 uint8_t enable_acg_gb_fuse_table;
3066 uint8_t uvdip_min_ver;
3067 uint8_t uvdip_max_ver;
3068 uint8_t vceip_min_ver;
3069 uint8_t vceip_max_ver;
3094 uint8_t umcip_min_ver;
3095 uint8_t umcip_max_ver;
3096 uint8_t vram_type; //enum of atom_dgpu_vram_type
3097 uint8_t umc_config;
3121 uint8_t umcip_min_ver;
3122 uint8_t umcip_max_ver;
3123 uint8_t vram_type; //enum of atom_dgpu_vram_type
3124 uint8_t umc_config;
3141 uint8_t umcip_min_ver;
3142 uint8_t umcip_max_ver;
3143 uint8_t vram_type; //enum of atom_dgpu_vram_type
3144 uint8_t umc_config;
3166 uint8_t umcip_min_ver;
3167 uint8_t umcip_max_ver;
3168 uint8_t vram_type;
3169 uint8_t umc_config;
3175 uint8_t channel_num;
3176 uint8_t channel_width;
3177 uint8_t channel_reserve[2];
3178 uint8_t umc_info_reserved[16];
3194 uint8_t ext_memory_id; // Current memory module ID
3195 uint8_t memory_type; // enum of atom_dgpu_vram_type
3196 uint8_t channel_num; // Number of mem. channels supported in this module
3197 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3198 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3199 uint8_t tunningset_id; // MC phy registers set per.
3200 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3201 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3202 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
3203 uint8_t vram_rsd2; // reserved
3217 uint8_t vram_module_num; // indicate number of VRAM module
3218 uint8_t umcip_min_ver;
3219 uint8_t umcip_max_ver;
3220 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3230 uint8_t density;
3231 uint8_t tunningset_id;
3232 uint8_t ext_memory_id;
3233 uint8_t dram_vendor_id;
3252 uint8_t vram_module_num;
3253 uint8_t umcip_min_ver;
3254 uint8_t umcip_max_ver;
3255 uint8_t mc_phy_tile_num;
3256 uint8_t memory_type;
3257 uint8_t channel_num;
3258 uint8_t channel_width;
3259 uint8_t reserved1;
3317 uint8_t ext_memory_id; // Current memory module ID
3318 uint8_t memory_type; // enum of atom_dgpu_vram_type
3319 uint8_t channel_num; // Number of mem. channels supported in this module
3320 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3321 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3322 uint8_t tunningset_id; // MC phy registers set per
3323 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3324 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3325 uint8_t vram_flags; // bit0= bankgroup enable
3326 uint8_t vram_rsd2; // reserved
3344 uint8_t vram_module_num; // indicate number of VRAM module
3345 uint8_t umcip_min_ver;
3346 uint8_t umcip_max_ver;
3347 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3357 uint8_t ext_memory_id; // Current memory module ID
3358 uint8_t memory_type; // enum of atom_dgpu_vram_type
3359 uint8_t channel_num; // Number of mem. channels supported in this module
3360 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3361 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3362 uint8_t tunningset_id; // MC phy registers set per.
3364 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3365 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3366 uint8_t vram_flags; // bit0= bankgroup enable
3367 uint8_t vram_rsd2; // reserved
3380 uint8_t RL;
3381 uint8_t WL;
3382 uint8_t tRAS;
3383 uint8_t tRC;
3386 uint8_t tRFC;
3387 uint8_t tRFCpb;
3389 uint8_t tRREFD;
3390 uint8_t tRCDRD;
3391 uint8_t tRCDWR;
3392 uint8_t tRP;
3394 uint8_t tRRDS;
3395 uint8_t tRRDL;
3396 uint8_t tWR;
3397 uint8_t tWTRS;
3399 uint8_t tWTRL;
3400 uint8_t tFAW;
3401 uint8_t tCCDS;
3402 uint8_t tCCDL;
3404 uint8_t tCRCRL;
3405 uint8_t tCRCWL;
3406 uint8_t tCKE;
3407 uint8_t tCKSRE;
3409 uint8_t tCKSRX;
3410 uint8_t tRTPS;
3411 uint8_t tRTPL;
3412 uint8_t tMRD;
3414 uint8_t tMOD;
3415 uint8_t tXS;
3416 uint8_t tXHP;
3417 uint8_t tXSMRS;
3421 uint8_t tPD;
3422 uint8_t tXP;
3423 uint8_t tCPDED;
3424 uint8_t tACTPDE;
3426 uint8_t tPREPDE;
3427 uint8_t tREFPDE;
3428 uint8_t tMRSPDEN;
3429 uint8_t tRDSRE;
3431 uint8_t tWRSRE;
3432 uint8_t tPPD;
3433 uint8_t tCCDMW;
3434 uint8_t tWTRTR;
3436 uint8_t tLTLTR;
3437 uint8_t tREFTR;
3438 uint8_t VNDR;
3439 uint8_t reserved[9];
3454 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK
3468 uint8_t vram_module_num; // indicate number of VRAM module
3469 uint8_t umcip_min_ver;
3470 uint8_t umcip_max_ver;
3471 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3485 uint8_t vram_module_num;
3486 uint8_t umcip_min_ver;
3487 uint8_t umcip_max_ver;
3488 uint8_t mc_phy_tile_num;
3503 uint8_t voltage_type; //enum atom_voltage_type
3504 uint8_t voltage_mode; //enum atom_voltage_object_mode
3522 uint8_t regulator_id; //Indicate Voltage Regulator Id
3523 uint8_t i2c_id;
3524 uint8_t i2c_slave_addr;
3525 uint8_t i2c_control_offset;
3526 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
3527 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
3528 uint8_t reserved[2];
3549 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
3550 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
3551 uint8_t phase_delay_us; // phase delay in unit of micro second
3552 uint8_t reserved;
3560 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
3561 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
3562 uint8_t psi0_enable; //
3563 uint8_t maxvstep;
3564 uint8_t telemetry_offset;
3565 uint8_t telemetry_gain;
3572 uint8_t merged_powerrail_type; //enum atom_voltage_type
3573 uint8_t reserved[3];
3718 uint8_t voltagetype; /* enum atom_voltage_type */
3719 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
3767 uint8_t pll_ss_enable;
3768 uint8_t reserved;
3783 uint8_t reserved;
3784 uint8_t bitslen;
3802 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
3803 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3804 uint8_t command; // enum of atom_get_smu_clock_info_command
3805 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3983 uint8_t ucode_func_id;
3984 uint8_t ucode_reserved[3];
3999 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
4000 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
4002 uint8_t encoder_mode; // Encoder mode:
4003 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
4004 uint8_t crtc_id; // enum of atom_crtc_def
4005 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
4006 uint8_t reserved1[2];
4045 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
4046 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
4047 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
4048 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
4092 uint8_t crtc_id; // enum atom_crtc_def
4093 uint8_t blanking; // enum atom_blank_crtc_command
4109 uint8_t crtc_id; // enum atom_crtc_def
4110 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
4111 uint8_t padding[2];
4120 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
4121 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
4122 uint8_t padding[2];
4145 uint8_t h_border;
4146 uint8_t v_border;
4147 uint8_t crtc_id; // enum atom_crtc_def
4148 uint8_t encoder_mode; // atom_encode_mode_def
4149 uint8_t padding[2];
4158 uint8_t i2cspeed_khz;
4160 uint8_t regindex;
4161 uint8_t status; /* enum atom_process_i2c_flag */
4164 uint8_t flag; /* enum atom_process_i2c_status */
4165 uint8_t trans_bytes;
4166 uint8_t slave_addr;
4167 uint8_t i2c_id;
4195 uint8_t channelid;
4197 uint8_t reply_status;
4198 uint8_t aux_delay;
4200 uint8_t dataout_len;
4201 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
4211 uint8_t crtc_id; // enum atom_crtc_def
4212 uint8_t encoder_id; // enum atom_dig_def
4213 uint8_t encode_mode; // enum atom_encode_mode_def
4214 uint8_t dst_bpc; // enum atom_panel_bit_per_color
4264 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4265 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
4266 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4267 uint8_t lanenum; // Lane number
4269 uint8_t bitpercolor;
4270 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
4271 uint8_t reserved[2];
4276 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4277 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
4278 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4279 uint8_t lanenum; // Lane number
4280 uint8_t symclk_10khz; // Symbol Clock in 10Khz
4281 uint8_t hpd_sel;
4282 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4283 uint8_t reserved[2];
4288 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4289 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
4290 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
4291 uint8_t reserved1;
4297 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4298 uint8_t action; // = rest of generic encoder command which does not carry any parameters
4299 uint8_t reserved1[2];
4318 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
4319 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
4321 uint8_t digmode; // enum atom_encode_mode_def
4322 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
4324 uint8_t lanenum; // Lane number 1, 2, 4, 8
4326 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
4327 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4328 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
4329 uint8_t reserved;
4407 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
4408 uint8_t action; //
4409 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
4410 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
4411 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
4412 uint8_t hpd_id;
4460 uint8_t revision;
4461 uint8_t checksum;
4462 uint8_t oemId[6];
4463 uint8_t oemTableId[8]; //UINT64 OemTableId;
4471 uint8_t tableUUID[16]; //0x24
4492 uint8_t vbioscontent[1];
4497 uint8_t lib1content[1];