Lines Matching defs:pdd

71 		struct kfd_process_device *pdd = process->pdds[i];
73 & pdd->exception_status;
78 *event_status = pdd->exception_status;
79 *gpu_id = pdd->dev->id;
80 pdd->exception_status &= ~exception_clear_mask;
132 struct kfd_process_device *pdd = process->pdds[i];
134 if (pdd->dev != dev)
137 pdd->exception_status |= event_mask & KFD_EC_MASK_DEVICE;
140 if (!pdd->vm_fault_exc_data) {
141 pdd->vm_fault_exc_data = kmemdup(
145 if (!pdd->vm_fault_exc_data)
261 struct kfd_process_device *pdd = NULL;
267 pdd = p->pdds[i];
272 if (!pdd)
276 pdd->vm_fault_exc_data;
278 kfd_dqm_evict_pasid(pdd->dev->dqm, p->pasid);
279 kfd_signal_vm_fault_event(pdd->dev, p->pasid, NULL, data);
348 int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en)
350 uint32_t spi_dbg_cntl = pdd->spi_dbg_override | pdd->spi_dbg_launch_mode;
351 uint32_t flags = pdd->process->dbg_flags;
353 if (!kfd_dbg_is_per_vmid_supported(pdd->dev))
356 return amdgpu_mes_set_shader_debugger(pdd->dev->adev, pdd->proc_ctx_gpu_addr, spi_dbg_cntl,
357 pdd->watch_points, flags, sq_trap_en);
361 static int kfd_dbg_get_dev_watch_id(struct kfd_process_device *pdd, int *watch_id)
367 spin_lock(&pdd->dev->kfd->watch_points_lock);
371 if ((pdd->dev->kfd->alloc_watch_ids >> i) & 0x1)
374 pdd->alloc_watch_ids |= 0x1 << i;
375 pdd->dev->kfd->alloc_watch_ids |= 0x1 << i;
377 spin_unlock(&pdd->dev->kfd->watch_points_lock);
381 spin_unlock(&pdd->dev->kfd->watch_points_lock);
386 static void kfd_dbg_clear_dev_watch_id(struct kfd_process_device *pdd, int watch_id)
388 spin_lock(&pdd->dev->kfd->watch_points_lock);
391 if ((pdd->alloc_watch_ids >> watch_id) & 0x1) {
392 pdd->alloc_watch_ids &= ~(0x1 << watch_id);
393 pdd->dev->kfd->alloc_watch_ids &= ~(0x1 << watch_id);
396 spin_unlock(&pdd->dev->kfd->watch_points_lock);
399 static bool kfd_dbg_owns_dev_watch_id(struct kfd_process_device *pdd, int watch_id)
403 spin_lock(&pdd->dev->kfd->watch_points_lock);
405 ((pdd->alloc_watch_ids >> watch_id) & 0x1);
407 spin_unlock(&pdd->dev->kfd->watch_points_lock);
412 int kfd_dbg_trap_clear_dev_address_watch(struct kfd_process_device *pdd,
417 if (!kfd_dbg_owns_dev_watch_id(pdd, watch_id))
420 if (!pdd->dev->kfd->shared_resources.enable_mes) {
421 r = debug_lock_and_unmap(pdd->dev->dqm);
426 amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
427 pdd->watch_points[watch_id] = pdd->dev->kfd2kgd->clear_address_watch(
428 pdd->dev->adev,
430 amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
432 if (!pdd->dev->kfd->shared_resources.enable_mes)
433 r = debug_map_and_unlock(pdd->dev->dqm);
435 r = kfd_dbg_set_mes_debug_mode(pdd, true);
437 kfd_dbg_clear_dev_watch_id(pdd, watch_id);
442 int kfd_dbg_trap_set_dev_address_watch(struct kfd_process_device *pdd,
448 int xcc_id, r = kfd_dbg_get_dev_watch_id(pdd, watch_id);
449 uint32_t xcc_mask = pdd->dev->xcc_mask;
454 if (!pdd->dev->kfd->shared_resources.enable_mes) {
455 r = debug_lock_and_unmap(pdd->dev->dqm);
457 kfd_dbg_clear_dev_watch_id(pdd, *watch_id);
462 amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
464 pdd->watch_points[*watch_id] = pdd->dev->kfd2kgd->set_address_watch(
465 pdd->dev->adev,
470 pdd->dev->vm_info.last_vmid_kfd,
472 amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
474 if (!pdd->dev->kfd->shared_resources.enable_mes)
475 r = debug_map_and_unlock(pdd->dev->dqm);
477 r = kfd_dbg_set_mes_debug_mode(pdd, true);
481 kfd_dbg_clear_dev_watch_id(pdd, *watch_id);
511 struct kfd_process_device *pdd = target->pdds[i];
513 if (!kfd_dbg_is_per_vmid_supported(pdd->dev))
516 if (!pdd->dev->kfd->shared_resources.enable_mes)
517 r = debug_refresh_runlist(pdd->dev->dqm);
519 r = kfd_dbg_set_mes_debug_mode(pdd, true);
534 struct kfd_process_device *pdd = target->pdds[i];
536 if (!kfd_dbg_is_per_vmid_supported(pdd->dev))
539 if (!pdd->dev->kfd->shared_resources.enable_mes)
540 debug_refresh_runlist(pdd->dev->dqm);
542 kfd_dbg_set_mes_debug_mode(pdd, true);
553 * If unwind == true, how far down the pdd list we need
576 struct kfd_process_device *pdd = target->pdds[i];
579 * enable calls on the pdd list, we need to stop now
585 kfd_process_set_trap_debug_flag(&pdd->qpd, false);
588 if (kfd_dbg_is_rlc_restore_supported(pdd->dev))
589 amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
590 pdd->spi_dbg_override =
591 pdd->dev->kfd2kgd->disable_debug_trap(
592 pdd->dev->adev,
594 pdd->dev->vm_info.last_vmid_kfd);
595 amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
597 if (!kfd_dbg_is_per_vmid_supported(pdd->dev) &&
598 release_debug_trap_vmid(pdd->dev->dqm, &pdd->qpd))
599 pr_err("Failed to release debug vmid on [%i]\n", pdd->dev->id);
601 if (!pdd->dev->kfd->shared_resources.enable_mes)
602 debug_refresh_runlist(pdd->dev->dqm);
604 kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev));
617 struct kfd_process_device *pdd = target->pdds[i];
619 kfd_process_drain_interrupts(pdd);
621 pdd->exception_status = 0;
674 struct kfd_process_device *pdd = target->pdds[i];
676 if (!kfd_dbg_is_per_vmid_supported(pdd->dev)) {
677 r = reserve_debug_trap_vmid(pdd->dev->dqm, &pdd->qpd);
695 amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
696 if (!(kfd_dbg_is_rlc_restore_supported(pdd->dev) ||
698 pdd->dev->kfd2kgd->enable_debug_trap(pdd->dev->adev, true,
699 pdd->dev->vm_info.last_vmid_kfd);
701 pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap(
702 pdd->dev->adev,
704 pdd->dev->vm_info.last_vmid_kfd);
706 if (kfd_dbg_is_rlc_restore_supported(pdd->dev))
707 amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
716 kfd_process_set_trap_debug_flag(&pdd->qpd, true);
718 if (!pdd->dev->kfd->shared_resources.enable_mes)
719 r = debug_refresh_runlist(pdd->dev->dqm);
721 r = kfd_dbg_set_mes_debug_mode(pdd, true);
752 struct kfd_process_device *pdd = target->pdds[i];
754 if (!KFD_IS_SOC15(pdd->dev))
757 if (pdd->qpd.num_gws && (!kfd_dbg_has_gws_support(pdd->dev) ||
758 kfd_dbg_has_cwsr_workaround(pdd->dev)))
805 struct kfd_process_device *pdd = p->pdds[i];
806 int err = pdd->dev->kfd2kgd->validate_trap_override_request(
807 pdd->dev->adev,
839 struct kfd_process_device *pdd = target->pdds[i];
841 amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
842 pdd->spi_dbg_override = pdd->dev->kfd2kgd->set_wave_launch_trap_override(
843 pdd->dev->adev,
844 pdd->dev->vm_info.last_vmid_kfd,
849 pdd->spi_dbg_override);
850 amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
852 if (!pdd->dev->kfd->shared_resources.enable_mes)
853 r = debug_refresh_runlist(pdd->dev->dqm);
855 r = kfd_dbg_set_mes_debug_mode(pdd, true);
875 struct kfd_process_device *pdd = target->pdds[i];
877 amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
878 pdd->spi_dbg_launch_mode = pdd->dev->kfd2kgd->set_wave_launch_mode(
879 pdd->dev->adev,
881 pdd->dev->vm_info.last_vmid_kfd);
882 amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
884 if (!pdd->dev->kfd->shared_resources.enable_mes)
885 r = debug_refresh_runlist(pdd->dev->dqm);
887 r = kfd_dbg_set_mes_debug_mode(pdd, true);
922 struct kfd_process_device *pdd = target->pdds[i];
923 struct qcm_process_device *qpd = &pdd->qpd;
947 struct kfd_process_device *pdd = NULL;
951 pdd = target->pdds[i];
952 if (pdd->dev->id == source_id) {
963 if (!(pdd->exception_status & KFD_EC_MASK(exception_code))) {
969 copy_size = min((size_t)(*info_size), pdd->vm_fault_exc_data_size);
971 if (copy_to_user(info, pdd->vm_fault_exc_data, copy_size)) {
975 actual_info_size = pdd->vm_fault_exc_data_size;
977 kfree(pdd->vm_fault_exc_data);
978 pdd->vm_fault_exc_data = NULL;
979 pdd->vm_fault_exc_data_size = 0;
982 exception_status_ptr = &pdd->exception_status;
1040 /* Run over all pdd of the process */
1042 struct kfd_process_device *pdd = target->pdds[i];
1043 struct kfd_topology_device *topo_dev = kfd_topology_device_by_id(pdd->dev->id);
1045 device_info.gpu_id = pdd->dev->id;
1046 device_info.exception_status = pdd->exception_status;
1047 device_info.lds_base = pdd->lds_base;
1048 device_info.lds_limit = pdd->lds_limit;
1049 device_info.scratch_base = pdd->scratch_base;
1050 device_info.scratch_limit = pdd->scratch_limit;
1051 device_info.gpuvm_base = pdd->gpuvm_base;
1052 device_info.gpuvm_limit = pdd->gpuvm_limit;
1056 device_info.revision_id = pdd->dev->adev->pdev->revision;
1057 device_info.subsystem_vendor_id = pdd->dev->adev->pdev->subsystem_vendor;
1058 device_info.subsystem_device_id = pdd->dev->adev->pdev->subsystem_device;
1059 device_info.fw_version = pdd->dev->kfd->mec_fw_version;
1068 device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask);
1073 pdd->exception_status &= ~exception_clear_mask;
1111 struct kfd_process_device *pdd = target->pdds[i];
1113 found_mask |= pdd->exception_status;