Lines Matching defs:args
177 struct kfd_ioctl_get_version_args *args = data;
179 args->major_version = KFD_IOCTL_MAJOR_VERSION;
180 args->minor_version = KFD_IOCTL_MINOR_VERSION;
186 struct kfd_ioctl_create_queue_args *args)
193 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
198 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
203 if ((args->ring_base_address) &&
204 (!access_ok((const void __user *) args->ring_base_address,
210 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
215 if (!access_ok((const void __user *) args->read_pointer_address,
221 if (!access_ok((const void __user *) args->write_pointer_address,
227 if (args->eop_buffer_address &&
228 !access_ok((const void __user *) args->eop_buffer_address,
234 if (args->ctx_save_restore_address &&
235 !access_ok((const void __user *) args->ctx_save_restore_address,
243 q_properties->queue_percent = args->queue_percentage & 0xFF;
245 q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
246 q_properties->priority = args->queue_priority;
247 q_properties->queue_address = args->ring_base_address;
248 q_properties->queue_size = args->ring_size;
249 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
250 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
251 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
252 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
254 args->ctx_save_restore_address;
255 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
256 q_properties->ctl_stack_size = args->ctl_stack_size;
257 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
258 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
260 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
262 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)
267 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
273 q_properties->queue_percent, args->queue_percentage);
276 q_properties->priority, args->queue_priority);
279 q_properties->queue_address, args->ring_base_address);
282 q_properties->queue_size, args->ring_size);
301 struct kfd_ioctl_create_queue_args *args = data;
314 err = set_queue_properties_from_user(&q_properties, args);
318 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
322 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
324 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
359 wptr_vm, args->write_pointer_address >> PAGE_SHIFT);
390 args->queue_id = queue_id;
394 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
395 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
400 args->doorbell_offset |= doorbell_offset_in_process;
404 pr_debug("Queue id %d was created successfully\n", args->queue_id);
407 args->ring_base_address);
410 args->read_pointer_address);
413 args->write_pointer_address);
432 struct kfd_ioctl_destroy_queue_args *args = data;
435 args->queue_id,
440 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
450 struct kfd_ioctl_update_queue_args *args = data;
458 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
463 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
468 if ((args->ring_base_address) &&
469 (!access_ok((const void __user *) args->ring_base_address,
475 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
480 properties.queue_address = args->ring_base_address;
481 properties.queue_size = args->ring_size;
482 properties.queue_percent = args->queue_percentage & 0xFF;
484 properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
485 properties.priority = args->queue_priority;
488 args->queue_id, p->pasid);
492 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties);
504 struct kfd_ioctl_set_cu_mask_args *args = data;
506 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
507 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
509 if ((args->num_cu_mask % 32) != 0) {
511 args->num_cu_mask);
515 minfo.cu_mask.count = args->num_cu_mask;
544 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo);
556 struct kfd_ioctl_get_queue_wave_state_args *args = data;
561 r = pqm_get_wave_state(&p->pqm, args->queue_id,
562 (void __user *)args->ctl_stack_address,
563 &args->ctl_stack_used_size,
564 &args->save_area_used_size);
574 struct kfd_ioctl_set_memory_policy_args *args = data;
579 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
580 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
584 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
585 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
590 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
592 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
603 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
607 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
614 (void __user *)args->alternate_aperture_base,
615 args->alternate_aperture_size))
628 struct kfd_ioctl_set_trap_handler_args *args = data;
634 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
646 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr);
683 struct kfd_ioctl_get_clock_counters_args *args = data;
687 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
691 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev);
694 args->gpu_clock_counter = 0;
697 args->cpu_clock_counter = ktime_get_raw_ns();
698 args->system_clock_counter = ktime_get_boottime_ns();
701 args->system_clock_freq = 1000000000;
710 struct kfd_ioctl_get_process_apertures_args *args = data;
716 args->num_of_nodes = 0;
724 &args->process_apertures[args->num_of_nodes];
734 "node id %u\n", args->num_of_nodes);
750 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS)
761 struct kfd_ioctl_get_process_apertures_new_args *args = data;
768 if (args->num_of_nodes == 0) {
773 args->num_of_nodes = p->n_pdds;
778 * nodes, but not more than args->num_of_nodes as that is
781 pa = kcalloc(args->num_of_nodes, sizeof(struct kfd_process_device_apertures),
789 args->num_of_nodes = 0;
795 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) {
823 args->num_of_nodes = i;
825 (void __user *)args->kfd_process_device_apertures_ptr,
839 struct kfd_ioctl_create_event_args *args = data;
846 if (args->event_page_offset) {
848 err = kfd_kmap_event_page(p, args->event_page_offset);
854 err = kfd_event_create(filp, p, args->event_type,
855 args->auto_reset != 0, args->node_id,
856 &args->event_id, &args->event_trigger_data,
857 &args->event_page_offset,
858 &args->event_slot_index);
860 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__);
867 struct kfd_ioctl_destroy_event_args *args = data;
869 return kfd_event_destroy(p, args->event_id);
875 struct kfd_ioctl_set_event_args *args = data;
877 return kfd_set_event(p, args->event_id);
883 struct kfd_ioctl_reset_event_args *args = data;
885 return kfd_reset_event(p, args->event_id);
891 struct kfd_ioctl_wait_events_args *args = data;
893 return kfd_wait_on_events(p, args->num_events,
894 (void __user *)args->events_ptr,
895 (args->wait_for_all != 0),
896 &args->timeout, &args->wait_result);
901 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
907 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
920 pdd->qpd.sh_hidden_private_base = args->va_addr;
927 dev->adev, args->va_addr, pdd->qpd.vmid);
940 struct kfd_ioctl_get_tile_config_args *args = data;
946 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
953 args->gb_addr_config = config.gb_addr_config;
954 args->num_banks = config.num_banks;
955 args->num_ranks = config.num_ranks;
957 if (args->num_tile_configs > config.num_tile_configs)
958 args->num_tile_configs = config.num_tile_configs;
959 err = copy_to_user((void __user *)args->tile_config_ptr,
961 args->num_tile_configs * sizeof(uint32_t));
963 args->num_tile_configs = 0;
967 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
968 args->num_macro_tile_configs =
970 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
972 args->num_macro_tile_configs * sizeof(uint32_t));
974 args->num_macro_tile_configs = 0;
984 struct kfd_ioctl_acquire_vm_args *args = data;
989 drm_file = fget(args->drm_fd);
994 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1045 struct kfd_ioctl_get_available_memory_args *args = data;
1046 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id);
1050 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev,
1059 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1065 uint64_t offset = args->mmap_offset;
1066 uint32_t flags = args->flags;
1068 if (args->size == 0)
1079 args->va_addr >> PAGE_SHIFT,
1080 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) {
1082 args->va_addr);
1092 args->mmap_offset >> PAGE_SHIFT,
1093 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) {
1095 args->mmap_offset);
1103 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1126 if (args->size != kfd_doorbell_process_slice(dev->kfd)) {
1136 if (args->size != PAGE_SIZE) {
1148 dev->adev, args->va_addr, args->size,
1163 uint64_t size = args->size;
1172 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1173 args->mmap_offset = offset;
1179 args->mmap_offset = KFD_MMAP_TYPE_MMIO
1180 | KFD_MMAP_GPU_ID(args->gpu_id);
1197 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1208 if (p->signal_handle && (p->signal_handle == args->handle)) {
1214 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1222 pdd, GET_IDR_HANDLE(args->handle));
1236 pdd, GET_IDR_HANDLE(args->handle));
1249 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1257 if (!args->n_devices) {
1261 if (args->n_success > args->n_devices) {
1266 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1272 (void __user *)args->device_ids_array_ptr,
1273 args->n_devices * sizeof(*devices_arr));
1280 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1294 GET_IDR_HANDLE(args->handle));
1300 for (i = args->n_success; i < args->n_devices; i++) {
1330 args->n_success = i+1;
1342 for (i = 0; i < args->n_devices; i++) {
1367 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1374 if (!args->n_devices) {
1378 if (args->n_success > args->n_devices) {
1383 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1389 (void __user *)args->device_ids_array_ptr,
1390 args->n_devices * sizeof(*devices_arr));
1397 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1404 GET_IDR_HANDLE(args->handle));
1410 for (i = args->n_success; i < args->n_devices; i++) {
1420 i, args->n_devices);
1423 args->n_success = i+1;
1437 for (i = 0; i < args->n_devices; i++) {
1470 struct kfd_ioctl_alloc_queue_gws_args *args = data;
1475 q = pqm_get_user_queue(&p->pqm, args->queue_id);
1500 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1503 args->first_gws = 0;
1514 struct kfd_ioctl_get_dmabuf_info_args *args = data;
1530 if (args->metadata_ptr) {
1531 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL);
1537 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd,
1538 &dmabuf_adev, &args->size,
1539 metadata_buffer, args->metadata_size,
1540 &args->metadata_size, &flags, &xcp_id);
1545 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id;
1547 args->gpu_id = dev->id;
1548 args->flags = flags;
1552 r = copy_to_user((void __user *)args->metadata_ptr,
1553 metadata_buffer, args->metadata_size);
1567 struct kfd_ioctl_import_dmabuf_args *args = data;
1575 dmabuf = dma_buf_get(args->dmabuf_fd);
1580 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1593 args->va_addr, pdd->drm_priv,
1608 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1624 struct kfd_ioctl_export_dmabuf_args *args = data;
1631 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1644 GET_IDR_HANDLE(args->handle));
1655 ret = dma_buf_fd(dmabuf, args->flags);
1663 args->dmabuf_fd = ret;
1677 struct kfd_ioctl_smi_events_args *args = data;
1682 pdd = kfd_process_device_data_by_id(p, args->gpuid);
1687 return kfd_smi_event_open(pdd->dev, &args->anon_fd);
1695 struct kfd_ioctl_set_xnack_mode_args *args = data;
1699 if (args->xnack_enabled >= 0) {
1706 if (p->xnack_enabled == args->xnack_enabled)
1709 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) {
1714 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled);
1716 args->xnack_enabled = p->xnack_enabled;
1727 struct kfd_ioctl_svm_args *args = data;
1731 args->start_addr, args->size, args->op, args->nattr);
1733 if ((args->start_addr & ~LINUX_PAGE_MASK) || (args->size & ~LINUX_PAGE_MASK))
1735 if (!args->start_addr || !args->size)
1738 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr,
1739 args->attrs);
2055 struct kfd_ioctl_criu_args *args)
2061 if (!args->devices || !args->bos || !args->priv_data)
2084 if (num_devices != args->num_devices ||
2085 num_bos != args->num_bos ||
2086 num_objects != args->num_objects ||
2087 priv_size != args->priv_data_size) {
2094 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset);
2098 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices,
2099 (uint8_t __user *)args->priv_data, &priv_offset);
2111 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,
2116 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,
2121 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);
2129 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
2130 (uint8_t __user *)args->priv_data, &bo_priv_offset);
2143 struct kfd_ioctl_criu_args *args,
2154 (void __user *)(args->priv_data + *priv_offset),
2184 struct kfd_ioctl_criu_args *args,
2193 if (args->num_devices != p->n_pdds)
2196 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size)
2199 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL);
2203 ret = copy_from_user(device_buckets, (void __user *)args->devices,
2204 args->num_devices * sizeof(*device_buckets));
2211 for (i = 0; i < args->num_devices; i++) {
2284 *priv_offset += args->num_devices * sizeof(*device_privs);
2425 struct kfd_ioctl_criu_args *args,
2434 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size)
2440 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL);
2444 ret = copy_from_user(bo_buckets, (void __user *)args->bos,
2445 args->num_bos * sizeof(*bo_buckets));
2452 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL);
2458 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset,
2459 args->num_bos * sizeof(*bo_privs));
2465 *priv_offset += args->num_bos * sizeof(*bo_privs);
2468 for (; i < args->num_bos; i++) {
2477 ret = copy_to_user((void __user *)args->bos,
2479 (args->num_bos * sizeof(*bo_buckets)));
2496 struct kfd_ioctl_criu_args *args,
2507 for (i = 0; i < args->num_objects; i++) {
2515 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset));
2523 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data,
2529 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data,
2535 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data,
2552 struct kfd_ioctl_criu_args *args)
2558 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size);
2560 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size ||
2561 !args->num_devices || !args->num_bos)
2575 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size);
2579 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size);
2583 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size);
2587 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size);
2591 if (priv_offset != args->priv_data_size) {
2608 struct kfd_ioctl_criu_args *args)
2632 struct kfd_ioctl_criu_args *args)
2639 args->pid);
2641 pid = find_get_pid(args->pid);
2643 pr_err("Cannot find pid info for %i\n", args->pid);
2653 pr_debug("Cannot find process info for %i\n", args->pid);
2660 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid);
2666 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid);
2677 struct kfd_ioctl_criu_args *args)
2695 args->pid = task_pid_nr_ns(p->lead_thread,
2698 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos,
2699 &args->num_objects, &args->priv_data_size);
2704 args->num_devices, args->num_bos, args->num_objects,
2705 args->priv_data_size);
2718 struct kfd_ioctl_criu_args *args = data;
2721 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op);
2722 switch (args->op) {
2724 ret = criu_process_info(filep, p, args);
2727 ret = criu_checkpoint(filep, p, args);
2730 ret = criu_unpause(filep, p, args);
2733 ret = criu_restore(filep, p, args);
2736 ret = criu_resume(filep, p, args);
2739 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op);
2745 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret);
2879 struct kfd_ioctl_runtime_enable_args *args = data;
2884 if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK)
2885 r = runtime_enable(p, args->r_debug,
2886 !!(args->mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK));
2897 struct kfd_ioctl_dbg_trap_args *args = data;
2910 pid = find_get_pid(args->pid);
2912 pr_debug("Cannot find pid info for %i\n", args->pid);
2929 if (args->op == KFD_IOC_DBG_TRAP_ENABLE) {
2943 pr_debug("Cannot find process PID %i to debug\n", args->pid);
2950 if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE
2952 pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid);
2962 if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) {
2963 pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op);
2969 (args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE ||
2970 args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE ||
2971 args->op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES ||
2972 args->op == KFD_IOC_DBG_TRAP_RESUME_QUEUES ||
2973 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2974 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH ||
2975 args->op == KFD_IOC_DBG_TRAP_SET_FLAGS)) {
2980 if (args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2981 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH) {
2983 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ?
2984 args->set_node_address_watch.gpu_id :
2985 args->clear_node_address_watch.gpu_id);
2994 switch (args->op) {
3000 args->enable.dbg_fd,
3001 (void __user *)args->enable.rinfo_ptr,
3002 &args->enable.rinfo_size);
3004 target->exception_enable_mask = args->enable.exception_mask;
3012 args->send_runtime_event.gpu_id,
3013 args->send_runtime_event.queue_id,
3014 args->send_runtime_event.exception_mask);
3018 args->set_exceptions_enabled.exception_mask);
3022 args->launch_override.override_mode,
3023 args->launch_override.enable_mask,
3024 args->launch_override.support_request_mask,
3025 &args->launch_override.enable_mask,
3026 &args->launch_override.support_request_mask);
3030 args->launch_mode.launch_mode);
3034 args->suspend_queues.num_queues,
3035 args->suspend_queues.grace_period,
3036 args->suspend_queues.exception_mask,
3037 (uint32_t *)args->suspend_queues.queue_array_ptr);
3041 r = resume_queues(target, args->resume_queues.num_queues,
3042 (uint32_t *)args->resume_queues.queue_array_ptr);
3046 args->set_node_address_watch.address,
3047 args->set_node_address_watch.mask,
3048 &args->set_node_address_watch.id,
3049 args->set_node_address_watch.mode);
3053 args->clear_node_address_watch.id);
3056 r = kfd_dbg_trap_set_flags(target, &args->set_flags.flags);
3060 &args->query_debug_event.queue_id,
3061 &args->query_debug_event.gpu_id,
3062 args->query_debug_event.exception_mask,
3063 &args->query_debug_event.exception_mask);
3067 args->query_exception_info.source_id,
3068 args->query_exception_info.exception_code,
3069 args->query_exception_info.clear_exception,
3070 (void __user *)args->query_exception_info.info_ptr,
3071 &args->query_exception_info.info_size);
3075 args->queue_snapshot.exception_mask,
3076 (void __user *)args->queue_snapshot.snapshot_buf_ptr,
3077 &args->queue_snapshot.num_queues,
3078 &args->queue_snapshot.entry_size);
3082 args->device_snapshot.exception_mask,
3083 (void __user *)args->device_snapshot.snapshot_buf_ptr,
3084 &args->device_snapshot.num_devices,
3085 &args->device_snapshot.entry_size);
3088 pr_err("Invalid option: %i\n", args->op);