Lines Matching full:me
75 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
89 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
106 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
123 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
161 if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
448 snprintf(ring->name, sizeof(ring->name), "uvd_%d", ring->me);
459 snprintf(ring->name, sizeof(ring->name), "uvd_enc_%d.%d", ring->me, i);
1185 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1188 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1191 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1194 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1198 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1201 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1204 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1255 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1261 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1265 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
1293 if (!ring->me)
1326 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
1330 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1333 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1336 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
1370 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1373 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1376 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1386 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1389 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1392 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
1395 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1422 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
1492 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1498 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1501 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1510 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1522 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1524 srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1552 if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1615 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1616 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1617 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1661 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1662 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1663 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1664 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1671 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1672 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1704 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1705 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1764 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1873 adev->uvd.inst[i].ring.me = i;
1887 adev->uvd.inst[j].ring_enc[i].me = j;