Lines Matching defs:ib
232 * @ib: IB object to schedule
239 struct amdgpu_ib *ib,
258 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
259 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
260 amdgpu_ring_write(ring, ib->length_dw);
913 struct amdgpu_ib ib;
922 memset(&ib, 0, sizeof(ib));
927 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
928 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
945 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
947 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
952 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
954 ib.ptr[1] = lower_32_bits(gpu_addr);
955 ib.ptr[2] = upper_32_bits(gpu_addr);
956 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
957 ib.ptr[4] = 0xDEADBEEF;
958 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
959 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
960 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
961 ib.length_dw = 8;
963 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
988 amdgpu_ib_free(adev, &ib, NULL);
1000 * @ib: indirect buffer to fill with commands
1007 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1013 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1015 ib->ptr[ib->length_dw++] = bytes - 1;
1016 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1017 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1018 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1019 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1020 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1027 * @ib: indirect buffer to fill with commands
1035 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1041 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1043 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1044 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1045 ib->ptr[ib->length_dw++] = ndw - 1;
1047 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1048 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1056 * @ib: indirect buffer to fill with commands
1065 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1071 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1072 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1073 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1074 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1075 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1076 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1077 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1078 ib->ptr[ib->length_dw++] = incr; /* increment size */
1079 ib->ptr[ib->length_dw++] = 0;
1080 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1086 * @ib: indirect buffer to fill with padding
1091 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1097 pad_count = (-ib->length_dw) & 0x7;
1100 ib->ptr[ib->length_dw++] =
1104 ib->ptr[ib->length_dw++] =
1783 * @ib: indirect buffer to copy to
1793 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1799 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1802 ib->ptr[ib->length_dw++] = byte_count - 1;
1803 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1804 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1805 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1806 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1807 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1813 * @ib: indirect buffer to fill
1820 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1825 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1826 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1827 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1828 ib->ptr[ib->length_dw++] = src_data;
1829 ib->ptr[ib->length_dw++] = byte_count - 1;