Lines Matching defs:sdma
555 for (i = 0; i < adev->sdma.num_instances; i++) {
580 for (i = 0; i < adev->sdma.num_instances; i++) {
737 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
741 if (sdma && sdma->burst_nop && (i == 0))
880 for (i = 0; i < adev->sdma.num_instances; i++) {
916 for (i = 0; i < adev->sdma.num_instances; i++) {
965 for (i = 0; i < adev->sdma.num_instances; i++) {
982 adev->sdma.instance[i].fw_version >= 14)
1006 if (adev->sdma.has_page_queue)
1010 for (i = 0; i < adev->sdma.num_instances; i++) {
1045 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1130 struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1303 for (i = 0; i < adev->sdma.num_instances; i++) {
1304 if (!adev->sdma.instance[i].fw)
1307 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1312 (adev->sdma.instance[i].fw->data +
1322 adev->sdma.instance[i].fw_version);
1354 /* enable sdma ring preemption */
1359 for (i = 0; i < adev->sdma.num_instances; i++) {
1364 if (adev->sdma.has_page_queue)
1389 for (i = 0; i < adev->sdma.num_instances; i++) {
1390 ring = &adev->sdma.instance[i].ring;
1396 if (adev->sdma.has_page_queue) {
1397 struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1630 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1636 if (sdma && sdma->burst_nop && (i == 0))
1699 uint fw_version = adev->sdma.instance[0].fw_version;
1721 DRM_ERROR("Failed to load sdma firmware!\n");
1728 adev->sdma.has_page_queue = false;
1730 adev->sdma.has_page_queue = true;
1752 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
1753 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count)
1754 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1767 for (i = 0; i < adev->sdma.num_instances; i++) {
1770 &adev->sdma.trap_irq);
1776 for (i = 0; i < adev->sdma.num_instances; i++) {
1779 &adev->sdma.ecc_irq);
1785 for (i = 0; i < adev->sdma.num_instances; i++) {
1788 &adev->sdma.vm_hole_irq);
1794 &adev->sdma.doorbell_invalid_irq);
1800 &adev->sdma.pool_timeout_irq);
1806 &adev->sdma.srbm_write_irq);
1811 for (i = 0; i < adev->sdma.num_instances; i++) {
1812 ring = &adev->sdma.instance[i].ring;
1831 snprintf(ring->name, sizeof(ring->name), "sdma%d", i);
1832 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1838 if (adev->sdma.has_page_queue) {
1839 ring = &adev->sdma.instance[i].page;
1866 &adev->sdma.trap_irq,
1875 dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1887 for (i = 0; i < adev->sdma.num_instances; i++) {
1888 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1889 if (adev->sdma.has_page_queue)
1890 amdgpu_ring_fini(&adev->sdma.instance[i].page);
1927 for (i = 0; i < adev->sdma.num_instances; i++) {
1928 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1975 for (i = 0; i < adev->sdma.num_instances; i++) {
1988 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1992 for (j = 0; j < adev->sdma.num_instances; j++) {
1993 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
1994 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
1997 if (j == adev->sdma.num_instances)
2039 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2043 amdgpu_fence_process(&adev->sdma.instance[instance].page);
2050 amdgpu_fence_process(&adev->sdma.instance[instance].page);
2093 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2122 if (instance < 0 || instance >= adev->sdma.num_instances) {
2123 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
2134 "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u "
2188 for (i = 0; i < adev->sdma.num_instances; i++) {
2202 for (i = 0; i < adev->sdma.num_instances; i++) {
2227 for (i = 0; i < adev->sdma.num_instances; i++) {
2228 /* 1-not override: enable sdma mem light sleep */
2235 for (i = 0; i < adev->sdma.num_instances; i++) {
2236 /* 0-override:disable sdma mem light sleep */
2384 for (i = 0; i < adev->sdma.num_instances; i++) {
2385 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
2386 adev->sdma.instance[i].ring.me = i;
2387 if (adev->sdma.has_page_queue) {
2388 adev->sdma.instance[i].page.funcs =
2390 adev->sdma.instance[i].page.me = i;
2427 adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
2428 adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
2430 switch (adev->sdma.num_instances) {
2433 adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
2434 adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
2435 adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
2436 adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
2441 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2442 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2443 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2444 adev->sdma.vm_hole_irq.funcs = &sdma_v4_0_vm_hole_irq_funcs;
2445 adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_0_doorbell_invalid_irq_funcs;
2446 adev->sdma.pool_timeout_irq.funcs = &sdma_v4_0_pool_timeout_irq_funcs;
2447 adev->sdma.srbm_write_irq.funcs = &sdma_v4_0_srbm_write_irq_funcs;
2515 if (adev->sdma.has_page_queue)
2516 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2518 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2535 for (i = 0; i < adev->sdma.num_instances; i++) {
2536 if (adev->sdma.has_page_queue)
2537 sched = &adev->sdma.instance[i].page.sched;
2539 sched = &adev->sdma.instance[i].ring.sched;
2542 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2554 /* the SDMA_EDC_COUNTER register in each sdma instance
2595 for (i = 0; i < adev->sdma.num_instances; i++) {
2609 for (i = 0; i < adev->sdma.num_instances; i++)
2631 adev->sdma.ras = &sdma_v4_0_ras;
2634 adev->sdma.ras = &sdma_v4_4_ras;