Lines Matching defs:ib
753 * @ib: IB object to schedule
760 struct amdgpu_ib *ib,
771 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
772 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
773 amdgpu_ring_write(ring, ib->length_dw);
1479 struct amdgpu_ib ib;
1493 memset(&ib, 0, sizeof(ib));
1495 AMDGPU_IB_POOL_DIRECT, &ib);
1499 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1501 ib.ptr[1] = lower_32_bits(gpu_addr);
1502 ib.ptr[2] = upper_32_bits(gpu_addr);
1503 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1504 ib.ptr[4] = 0xDEADBEEF;
1505 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1506 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1507 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1508 ib.length_dw = 8;
1510 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1528 amdgpu_ib_free(adev, &ib, NULL);
1539 * @ib: indirect buffer to fill with commands
1546 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1552 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1554 ib->ptr[ib->length_dw++] = bytes - 1;
1555 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1556 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1557 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1558 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1559 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1566 * @ib: indirect buffer to fill with commands
1574 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1580 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1582 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1583 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1584 ib->ptr[ib->length_dw++] = ndw - 1;
1586 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1587 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1595 * @ib: indirect buffer to fill with commands
1604 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1610 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1611 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1612 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1613 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1614 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1615 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1616 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1617 ib->ptr[ib->length_dw++] = incr; /* increment size */
1618 ib->ptr[ib->length_dw++] = 0;
1619 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1626 * @ib: indirect buffer to fill with padding
1628 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1634 pad_count = (-ib->length_dw) & 7;
1637 ib->ptr[ib->length_dw++] =
1641 ib->ptr[ib->length_dw++] =
2453 * @ib: indirect buffer to copy to
2463 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2469 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2472 ib->ptr[ib->length_dw++] = byte_count - 1;
2473 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2474 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2475 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2476 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2477 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2483 * @ib: indirect buffer to copy to
2490 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2495 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2496 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2497 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2498 ib->ptr[ib->length_dw++] = src_data;
2499 ib->ptr[ib->length_dw++] = byte_count - 1;