Lines Matching defs:instance

78 #define WREG32_SDMA(instance, offset, value) \
79 	WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
80 #define RREG32_SDMA(instance, offset) \
81 	RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
395 		u32 instance, u32 offset)
397 	switch (instance) {
584 			   for every SDMA instance */
982 		    adev->sdma.instance[i].fw_version >= 14)
1038  * @i: instance to resume
1045 	struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1123  * @i: instance to resume
1130 	struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1304 		if (!adev->sdma.instance[i].fw)
1307 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1312 			(adev->sdma.instance[i].fw->data +
1322 			    adev->sdma.instance[i].fw_version);
1390 		ring = &adev->sdma.instance[i].ring;
1397 			struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1699 	uint fw_version = adev->sdma.instance[0].fw_version;
1812 		ring = &adev->sdma.instance[i].ring;
1823 		 * On Arcturus, SDMA instance 5~7 has a different vmhub
1839 			ring = &adev->sdma.instance[i].page;
1888 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1890 			amdgpu_ring_fini(&adev->sdma.instance[i].page);
2030 	int instance;
2033 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2034 	if (instance < 0)
2035 		return instance;
2039 		amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2043 			amdgpu_fence_process(&adev->sdma.instance[instance].page);
2050 			amdgpu_fence_process(&adev->sdma.instance[instance].page);
2060 	int instance;
2069 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2070 	if (instance < 0)
2083 	int instance;
2087 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2088 	if (instance < 0)
2093 		drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2117 	int instance;
2121 	instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2122 	if (instance < 0 || instance >= adev->sdma.num_instances) {
2123 		dev_err(adev->dev, "sdma instance invalid %d\n", instance);
2136 		   instance, addr, entry->src_id, entry->ring_id, entry->vmid,
2385 		adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
2386 		adev->sdma.instance[i].ring.me = i;
2388 			adev->sdma.instance[i].page.funcs =
2390 			adev->sdma.instance[i].page.me = i;
2516 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2518 		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2537 			sched = &adev->sdma.instance[i].page.sched;
2539 			sched = &adev->sdma.instance[i].ring.sched;
2546 					uint32_t instance,
2554 		/* the SDMA_EDC_COUNTER register in each sdma instance
2563 				instance, sec_cnt);
2570 			uint32_t instance, void *ras_error_status)
2576 	reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2580 				instance, &sec_count);