Lines Matching full:data
242 uint32_t def, data; in nbio_v4_3_update_medium_grain_clock_gating() local
247 def = data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); in nbio_v4_3_update_medium_grain_clock_gating()
249 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | in nbio_v4_3_update_medium_grain_clock_gating()
256 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK | in nbio_v4_3_update_medium_grain_clock_gating()
264 if (def != data) in nbio_v4_3_update_medium_grain_clock_gating()
265 WREG32_SOC15(NBIO, 0, regCPM_CONTROL, data); in nbio_v4_3_update_medium_grain_clock_gating()
271 uint32_t def, data; in nbio_v4_3_update_medium_grain_light_sleep() local
277 def = data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); in nbio_v4_3_update_medium_grain_light_sleep()
279 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK; in nbio_v4_3_update_medium_grain_light_sleep()
281 data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK; in nbio_v4_3_update_medium_grain_light_sleep()
284 if (def != data) in nbio_v4_3_update_medium_grain_light_sleep()
285 WREG32_SOC15(NBIO, 0, regPCIE_CNTL2, data); in nbio_v4_3_update_medium_grain_light_sleep()
291 int data; in nbio_v4_3_get_clockgating_state() local
294 data = RREG32_SOC15(NBIO, 0, regCPM_CONTROL); in nbio_v4_3_get_clockgating_state()
295 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) in nbio_v4_3_get_clockgating_state()
299 data = RREG32_SOC15(NBIO, 0, regPCIE_CNTL2); in nbio_v4_3_get_clockgating_state()
300 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in nbio_v4_3_get_clockgating_state()
342 uint32_t data; in nbio_v4_3_init_registers() local
344 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2); in nbio_v4_3_init_registers()
345 data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK; in nbio_v4_3_init_registers()
346 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data); in nbio_v4_3_init_registers()
355 u32 data, rom_offset; in nbio_v4_3_get_rom_offset() local
357 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); in nbio_v4_3_get_rom_offset()
358 rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET); in nbio_v4_3_get_rom_offset()
366 uint32_t def, data; in nbio_v4_3_program_ltr() local
369 data = 0x35EB; in nbio_v4_3_program_ltr()
370 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; in nbio_v4_3_program_ltr()
371 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK; in nbio_v4_3_program_ltr()
372 if (def != data) in nbio_v4_3_program_ltr()
373 WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); in nbio_v4_3_program_ltr()
375 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2); in nbio_v4_3_program_ltr()
376 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; in nbio_v4_3_program_ltr()
377 if (def != data) in nbio_v4_3_program_ltr()
378 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data); in nbio_v4_3_program_ltr()
380 def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); in nbio_v4_3_program_ltr()
382 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; in nbio_v4_3_program_ltr()
384 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; in nbio_v4_3_program_ltr()
385 if (def != data) in nbio_v4_3_program_ltr()
386 WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); in nbio_v4_3_program_ltr()
393 uint32_t def, data; in nbio_v4_3_program_aspm() local
399 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL); in nbio_v4_3_program_aspm()
400 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; in nbio_v4_3_program_aspm()
401 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; in nbio_v4_3_program_aspm()
402 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; in nbio_v4_3_program_aspm()
403 if (def != data) in nbio_v4_3_program_aspm()
404 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data); in nbio_v4_3_program_aspm()
406 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7); in nbio_v4_3_program_aspm()
407 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; in nbio_v4_3_program_aspm()
408 if (def != data) in nbio_v4_3_program_aspm()
409 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL7, data); in nbio_v4_3_program_aspm()
411 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3); in nbio_v4_3_program_aspm()
412 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; in nbio_v4_3_program_aspm()
413 if (def != data) in nbio_v4_3_program_aspm()
414 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data); in nbio_v4_3_program_aspm()
416 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); in nbio_v4_3_program_aspm()
417 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; in nbio_v4_3_program_aspm()
418 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; in nbio_v4_3_program_aspm()
419 if (def != data) in nbio_v4_3_program_aspm()
420 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); in nbio_v4_3_program_aspm()
422 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); in nbio_v4_3_program_aspm()
423 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; in nbio_v4_3_program_aspm()
424 if (def != data) in nbio_v4_3_program_aspm()
425 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); in nbio_v4_3_program_aspm()
427 def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); in nbio_v4_3_program_aspm()
428 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; in nbio_v4_3_program_aspm()
429 if (def != data) in nbio_v4_3_program_aspm()
430 WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); in nbio_v4_3_program_aspm()
434 def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2); in nbio_v4_3_program_aspm()
435 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | in nbio_v4_3_program_aspm()
437 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; in nbio_v4_3_program_aspm()
438 if (def != data) in nbio_v4_3_program_aspm()
439 WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data); in nbio_v4_3_program_aspm()
441 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4); in nbio_v4_3_program_aspm()
442 data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK; in nbio_v4_3_program_aspm()
443 if (def != data) in nbio_v4_3_program_aspm()
444 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL4, data); in nbio_v4_3_program_aspm()
446 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL); in nbio_v4_3_program_aspm()
447 data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK; in nbio_v4_3_program_aspm()
448 if (def != data) in nbio_v4_3_program_aspm()
449 WREG32_SOC15(NBIO, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data); in nbio_v4_3_program_aspm()
453 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); in nbio_v4_3_program_aspm()
454 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; in nbio_v4_3_program_aspm()
455 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; in nbio_v4_3_program_aspm()
456 if (def != data) in nbio_v4_3_program_aspm()
457 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); in nbio_v4_3_program_aspm()
459 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); in nbio_v4_3_program_aspm()
460 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; in nbio_v4_3_program_aspm()
461 if (def != data) in nbio_v4_3_program_aspm()
462 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); in nbio_v4_3_program_aspm()
464 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL); in nbio_v4_3_program_aspm()
465 data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; in nbio_v4_3_program_aspm()
466 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; in nbio_v4_3_program_aspm()
467 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; in nbio_v4_3_program_aspm()
468 if (def != data) in nbio_v4_3_program_aspm()
469 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL, data); in nbio_v4_3_program_aspm()
471 def = data = RREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3); in nbio_v4_3_program_aspm()
472 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; in nbio_v4_3_program_aspm()
473 if (def != data) in nbio_v4_3_program_aspm()
474 WREG32_SOC15(NBIO, 0, regPCIE_LC_CNTL3, data); in nbio_v4_3_program_aspm()