232 	uint32_t def, data;  in nbio_v2_3_update_medium_grain_clock_gating()  local
237 	def = data = RREG32_PCIE(smnCPM_CONTROL);  in nbio_v2_3_update_medium_grain_clock_gating()
239 		data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |  in nbio_v2_3_update_medium_grain_clock_gating()
246 		data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |  in nbio_v2_3_update_medium_grain_clock_gating()
254 	if (def != data)  in nbio_v2_3_update_medium_grain_clock_gating()
255 		WREG32_PCIE(smnCPM_CONTROL, data);  in nbio_v2_3_update_medium_grain_clock_gating()
261 	uint32_t def, data;  in nbio_v2_3_update_medium_grain_light_sleep()  local
266 	def = data = RREG32_PCIE(smnPCIE_CNTL2);  in nbio_v2_3_update_medium_grain_light_sleep()
268 		data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |  in nbio_v2_3_update_medium_grain_light_sleep()
272 		data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |  in nbio_v2_3_update_medium_grain_light_sleep()
277 	if (def != data)  in nbio_v2_3_update_medium_grain_light_sleep()
278 		WREG32_PCIE(smnPCIE_CNTL2, data);  in nbio_v2_3_update_medium_grain_light_sleep()
284 	int data;  in nbio_v2_3_get_clockgating_state()  local
287 	data = RREG32_PCIE(smnCPM_CONTROL);  in nbio_v2_3_get_clockgating_state()
288 	if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)  in nbio_v2_3_get_clockgating_state()
292 	data = RREG32_PCIE(smnPCIE_CNTL2);  in nbio_v2_3_get_clockgating_state()
293 	if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)  in nbio_v2_3_get_clockgating_state()
334 	uint32_t def, data;  in nbio_v2_3_init_registers()  local
336 	def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);  in nbio_v2_3_init_registers()
337 	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);  in nbio_v2_3_init_registers()
338 	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);  in nbio_v2_3_init_registers()
340 	if (def != data)  in nbio_v2_3_init_registers()
341 		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);  in nbio_v2_3_init_registers()
355 	uint32_t def, data;  in nbio_v2_3_enable_aspm()  local
357 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);  in nbio_v2_3_enable_aspm()
361 		data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);  in nbio_v2_3_enable_aspm()
363 		data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;  in nbio_v2_3_enable_aspm()
366 			data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT  << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;  in nbio_v2_3_enable_aspm()
368 			data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;  in nbio_v2_3_enable_aspm()
370 		data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;  in nbio_v2_3_enable_aspm()
373 		data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;  in nbio_v2_3_enable_aspm()
375 		data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;  in nbio_v2_3_enable_aspm()
377 		data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;  in nbio_v2_3_enable_aspm()
380 	if (def != data)  in nbio_v2_3_enable_aspm()
381 		WREG32_PCIE(smnPCIE_LC_CNTL, data);  in nbio_v2_3_enable_aspm()
387 	uint32_t def, data;  in nbio_v2_3_program_ltr()  local
391 	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2);  in nbio_v2_3_program_ltr()
392 	data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;  in nbio_v2_3_program_ltr()
393 	if (def != data)  in nbio_v2_3_program_ltr()
394 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP2, data);  in nbio_v2_3_program_ltr()
396 	def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);  in nbio_v2_3_program_ltr()
397 	data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;  in nbio_v2_3_program_ltr()
398 	if (def != data)  in nbio_v2_3_program_ltr()
399 		WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);  in nbio_v2_3_program_ltr()
401 	def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);  in nbio_v2_3_program_ltr()
402 	data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;  in nbio_v2_3_program_ltr()
403 	if (def != data)  in nbio_v2_3_program_ltr()
404 		WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);  in nbio_v2_3_program_ltr()
411 	uint32_t def, data;  in nbio_v2_3_program_aspm()  local
413 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);  in nbio_v2_3_program_aspm()
414 	data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;  in nbio_v2_3_program_aspm()
415 	data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;  in nbio_v2_3_program_aspm()
416 	data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;  in nbio_v2_3_program_aspm()
417 	if (def != data)  in nbio_v2_3_program_aspm()
418 		WREG32_PCIE(smnPCIE_LC_CNTL, data);  in nbio_v2_3_program_aspm()
420 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);  in nbio_v2_3_program_aspm()
421 	data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;  in nbio_v2_3_program_aspm()
422 	if (def != data)  in nbio_v2_3_program_aspm()
423 		WREG32_PCIE(smnPCIE_LC_CNTL7, data);  in nbio_v2_3_program_aspm()
425 	def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);  in nbio_v2_3_program_aspm()
426 	data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;  in nbio_v2_3_program_aspm()
427 	if (def != data)  in nbio_v2_3_program_aspm()
428 		WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);  in nbio_v2_3_program_aspm()
430 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);  in nbio_v2_3_program_aspm()
431 	data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;  in nbio_v2_3_program_aspm()
432 	if (def != data)  in nbio_v2_3_program_aspm()
433 		WREG32_PCIE(smnPCIE_LC_CNTL3, data);  in nbio_v2_3_program_aspm()
435 	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);  in nbio_v2_3_program_aspm()
436 	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;  in nbio_v2_3_program_aspm()
437 	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;  in nbio_v2_3_program_aspm()
438 	if (def != data)  in nbio_v2_3_program_aspm()
439 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data);  in nbio_v2_3_program_aspm()
441 	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);  in nbio_v2_3_program_aspm()
442 	data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;  in nbio_v2_3_program_aspm()
443 	if (def != data)  in nbio_v2_3_program_aspm()
444 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);  in nbio_v2_3_program_aspm()
446 	def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);  in nbio_v2_3_program_aspm()
447 	data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;  in nbio_v2_3_program_aspm()
448 	if (def != data)  in nbio_v2_3_program_aspm()
449 		WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);  in nbio_v2_3_program_aspm()
453 	def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);  in nbio_v2_3_program_aspm()
454 	data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |  in nbio_v2_3_program_aspm()
456 	data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;  in nbio_v2_3_program_aspm()
457 	if (def != data)  in nbio_v2_3_program_aspm()
458 		WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);  in nbio_v2_3_program_aspm()
460 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);  in nbio_v2_3_program_aspm()
461 	data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |  in nbio_v2_3_program_aspm()
463 	if (def != data)  in nbio_v2_3_program_aspm()
464 		WREG32_PCIE(smnPCIE_LC_CNTL6, data);  in nbio_v2_3_program_aspm()
471 	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);  in nbio_v2_3_program_aspm()
472 	data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;  in nbio_v2_3_program_aspm()
473 	data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;  in nbio_v2_3_program_aspm()
474 	if (def != data)  in nbio_v2_3_program_aspm()
475 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3, data);  in nbio_v2_3_program_aspm()
477 	def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5);  in nbio_v2_3_program_aspm()
478 	data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;  in nbio_v2_3_program_aspm()
479 	if (def != data)  in nbio_v2_3_program_aspm()
480 		WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);  in nbio_v2_3_program_aspm()
482 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);  in nbio_v2_3_program_aspm()
483 	data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;  in nbio_v2_3_program_aspm()
485 		data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT  << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;  in nbio_v2_3_program_aspm()
487 		data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;  in nbio_v2_3_program_aspm()
488 	data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;  in nbio_v2_3_program_aspm()
489 	if (def != data)  in nbio_v2_3_program_aspm()
490 		WREG32_PCIE(smnPCIE_LC_CNTL, data);  in nbio_v2_3_program_aspm()
492 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);  in nbio_v2_3_program_aspm()
493 	data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;  in nbio_v2_3_program_aspm()
494 	if (def != data)  in nbio_v2_3_program_aspm()
495 		WREG32_PCIE(smnPCIE_LC_CNTL3, data);  in nbio_v2_3_program_aspm()
513 	 * Program PCIE_LC_CNTL6.LC_SPC_MODE_8GT to 0x2 (4 symbols per clock data)  in nbio_v2_3_apply_lc_spc_mode_wa()