Lines Matching defs:enable
123 * @enable: true - enable the interrupts, false - disable the interrupts
129 bool enable)
137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
139 if (enable) {
168 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
177 if (enable) {
194 * @enable: enable or disable interrupt ring buffers
198 static int ih_v6_0_toggle_interrupts(struct amdgpu_device *adev, bool enable)
206 r = ih_v6_0_toggle_ring_interrupts(adev, ih[i], enable);
258 * ih_v6_0_enable_ring - enable an ih ring buffer
311 * ih_v6_0_irq_init - init and enable the interrupt ring
316 * enable the RLC, disable interrupts, enable the IH
317 * ring buffer and enable it.
379 /* enable interrupts */
383 /* enable wptr force update for self int */
658 bool enable)
664 field_val = enable ? 0 : 1;
693 bool enable)
704 if (enable) {
719 /* re-enable power cntl */
737 /* re-enable power cntl*/
749 bool enable = (state == AMD_PG_STATE_GATE);
752 ih_v6_0_update_ih_mem_power_gating(adev, enable);