Lines Matching defs:wave
759 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
762 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
767 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
772 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
780 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
787 /* type 3 wave data */
789 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
790 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
791 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
792 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
793 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
794 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
795 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
796 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
797 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
798 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
799 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
800 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
801 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
802 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
803 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
807 uint32_t wave, uint32_t start,
813 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
818 uint32_t wave, uint32_t thread,
823 adev, wave, thread,
5331 /* Currently, there is a high possibility to get wave ID mismatch
5333 * different wave IDs than the GDS expects. This situation happens
5335 * The wave IDs generated by ME are also wrong after suspend/resume.
5338 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and