Lines Matching defs:resv
380 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
383 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
909 * @resv: fences we need to sync to
926 struct dma_resv *resv, uint64_t start, uint64_t last,
986 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1081 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv &&
1082 !dma_resv_trylock(bo->tbo.base.resv))
1086 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
1087 dma_resv_unlock(bo->tbo.base.resv);
1138 struct dma_resv *resv;
1145 resv = vm->root.bo->tbo.base.resv;
1149 resv = bo->tbo.base.resv;
1182 if (clear || (bo && bo->tbo.base.resv ==
1183 vm->root.bo->tbo.base.resv))
1213 resv, mapping->start, mapping->last,
1225 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1362 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1366 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1392 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1407 r = amdgpu_vm_update_range(adev, vm, false, false, true, resv,
1446 struct dma_resv *resv;
1466 resv = bo_va->base.bo->tbo.base.resv;
1470 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
1481 dma_resv_unlock(resv);
1524 dma_resv_assert_held(bo->tbo.base.resv);
1558 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1860 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1875 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1924 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
1951 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
1954 dma_resv_assert_held(bo->tbo.base.resv);
1955 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2010 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
2049 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2060 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2197 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2287 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2722 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);