Lines Matching defs:vcn
94 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name);
96 amdgpu_ucode_release(&adev->vcn.fw);
109 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
110 rw_init(&adev->vcn.vcn_pg_lock, "vcnpg");
111 rw_init(&adev->vcn.vcn1_jpeg1_workaround, "vcnwa");
112 atomic_set(&adev->vcn.total_submission_cnt, 0);
113 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
114 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
118 adev->vcn.indirect_sram = true;
132 adev->vcn.indirect_sram = false;
139 adev->vcn.using_unified_queue =
142 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
143 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
189 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
190 if (adev->vcn.harvest_config & (1 << i))
196 &adev->vcn.inst[i].vcpu_bo,
197 &adev->vcn.inst[i].gpu_addr,
198 &adev->vcn.inst[i].cpu_addr);
200 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
204 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
206 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
209 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
212 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
213 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
214 adev->vcn.inst[i].fw_shared.log_offset = log_offset;
217 if (adev->vcn.indirect_sram) {
221 &adev->vcn.inst[i].dpg_sram_bo,
222 &adev->vcn.inst[i].dpg_sram_gpu_addr,
223 &adev->vcn.inst[i].dpg_sram_cpu_addr);
238 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
239 if (adev->vcn.harvest_config & (1 << j))
243 &adev->vcn.inst[j].dpg_sram_bo,
244 &adev->vcn.inst[j].dpg_sram_gpu_addr,
245 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
247 kvfree(adev->vcn.inst[j].saved_bo);
249 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
250 &adev->vcn.inst[j].gpu_addr,
251 (void **)&adev->vcn.inst[j].cpu_addr);
253 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
255 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
256 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
259 amdgpu_ucode_release(&adev->vcn.fw);
260 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
261 mutex_destroy(&adev->vcn.vcn_pg_lock);
269 int vcn_config = adev->vcn.vcn_config[vcn_instance];
289 cancel_delayed_work_sync(&adev->vcn.idle_work);
296 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
297 if (adev->vcn.harvest_config & (1 << i))
299 if (adev->vcn.inst[i].vcpu_bo == NULL)
302 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
303 ptr = adev->vcn.inst[i].cpu_addr;
305 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
306 if (!adev->vcn.inst[i].saved_bo)
310 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
323 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
324 if (adev->vcn.harvest_config & (1 << i))
326 if (adev->vcn.inst[i].vcpu_bo == NULL)
329 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
330 ptr = adev->vcn.inst[i].cpu_addr;
332 if (adev->vcn.inst[i].saved_bo != NULL) {
334 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
337 kvfree(adev->vcn.inst[i].saved_bo);
338 adev->vcn.inst[i].saved_bo = NULL;
343 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
347 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
363 container_of(work, struct amdgpu_device, vcn.idle_work.work);
368 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
369 if (adev->vcn.harvest_config & (1 << j))
372 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
373 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
377 !adev->vcn.using_unified_queue) {
381 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
386 adev->vcn.pause_dpg_mode(adev, j, &new_state);
389 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
393 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
401 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
410 atomic_inc(&adev->vcn.total_submission_cnt);
412 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
419 mutex_lock(&adev->vcn.vcn_pg_lock);
425 !adev->vcn.using_unified_queue) {
429 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
435 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
436 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
438 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
444 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
446 mutex_unlock(&adev->vcn.vcn_pg_lock);
456 !adev->vcn.using_unified_queue)
457 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
459 atomic_dec(&ring->adev->vcn.total_submission_cnt);
461 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
475 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
479 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
483 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
544 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
546 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
548 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
551 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
714 if (adev->vcn.using_unified_queue)
727 if (adev->vcn.using_unified_queue) {
746 if (adev->vcn.using_unified_queue)
844 if (adev->vcn.using_unified_queue)
858 if (adev->vcn.using_unified_queue)
880 if (adev->vcn.using_unified_queue)
911 if (adev->vcn.using_unified_queue)
925 if (adev->vcn.using_unified_queue)
947 if (adev->vcn.using_unified_queue)
1039 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
1041 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1042 if (adev->vcn.harvest_config & (1 << i))
1051 adev->firmware.ucode[idx].fw = adev->vcn.fw;
1063 * debugfs for mapping vcn firmware log buffer.
1069 struct amdgpu_vcn_inst *vcn;
1075 vcn = file_inode(f)->i_private;
1076 if (!vcn)
1079 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1082 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1134 struct amdgpu_vcn_inst *vcn)
1142 debugfs_create_file_size(name, S_IFREG | 0444, root, vcn,
1148 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1151 volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1152 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1153 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1155 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1156 + vcn->fw_shared.log_offset;
1175 struct ras_common_if *ras_if = adev->vcn.ras_if;
1206 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1207 if (adev->vcn.harvest_config & (1 << i) ||
1208 !adev->vcn.inst[i].ras_poison_irq.funcs)
1211 r = amdgpu_irq_get(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
1228 if (!adev->vcn.ras)
1231 ras = adev->vcn.ras;
1234 dev_err(adev->dev, "Failed to register vcn ras block!\n");
1238 strlcpy(ras->ras_block.ras_comm.name, "vcn",
1242 adev->vcn.ras_if = &ras->ras_block.ras_comm;
1257 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1258 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1259 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr),