Lines Matching defs:op_input

772 	struct mes_misc_op_input op_input;
775 	op_input.op = MES_MISC_OP_READ_REG;
776 	op_input.read_reg.reg_offset = reg;
777 	op_input.read_reg.buffer_addr = adev->mes.read_val_gpu_addr;
784 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
797 	struct mes_misc_op_input op_input;
800 	op_input.op = MES_MISC_OP_WRITE_REG;
801 	op_input.write_reg.reg_offset = reg;
802 	op_input.write_reg.reg_value = val;
810 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
822 	struct mes_misc_op_input op_input;
825 	op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT;
826 	op_input.wrm_reg.reg0 = reg0;
827 	op_input.wrm_reg.reg1 = reg1;
828 	op_input.wrm_reg.ref = ref;
829 	op_input.wrm_reg.mask = mask;
837 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
848 	struct mes_misc_op_input op_input;
851 	op_input.op = MES_MISC_OP_WRM_REG_WAIT;
852 	op_input.wrm_reg.reg0 = reg;
853 	op_input.wrm_reg.ref = val;
854 	op_input.wrm_reg.mask = mask;
862 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
877 	struct mes_misc_op_input op_input = {0};
885 	op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;
886 	op_input.set_shader_debugger.process_context_addr = process_context_addr;
887 	op_input.set_shader_debugger.flags.u32all = flags;
890 	if (op_input.set_shader_debugger.flags.process_ctx_flush)
893 	op_input.set_shader_debugger.spi_gdbg_per_vmid_cntl = spi_gdbg_per_vmid_cntl;
894 	memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl,
895 			sizeof(op_input.set_shader_debugger.tcp_watch_cntl));
899 		op_input.set_shader_debugger.trap_en = trap_en;
903 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
915 	struct mes_misc_op_input op_input = {0};
923 	op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER;
924 	op_input.set_shader_debugger.process_context_addr = process_context_addr;
925 	op_input.set_shader_debugger.flags.process_ctx_flush = true;
929 	r = adev->mes.funcs->misc_op(&adev->mes, &op_input);