Lines Matching defs:mes
47 struct amdgpu_mes *mes = &adev->mes;
54 found = find_next_zero_bit(mes->doorbell_bitmap, mes->num_mes_dbs, offset);
55 if (found >= mes->num_mes_dbs) {
60 set_bit(found, mes->doorbell_bitmap);
63 *doorbell_index = mes->db_start_dw_offset + found * 2;
72 struct amdgpu_mes *mes = &adev->mes;
75 rel_index = (doorbell_index - mes->db_start_dw_offset) / 2;
76 old = test_and_clear_bit(rel_index, mes->doorbell_bitmap);
83 struct amdgpu_mes *mes = &adev->mes;
86 mes->doorbell_bitmap = bitmap_zalloc(PAGE_SIZE / sizeof(u32), GFP_KERNEL);
87 if (!mes->doorbell_bitmap) {
92 mes->num_mes_dbs = PAGE_SIZE / AMDGPU_ONE_DOORBELL_SIZE;
94 adev->mes.aggregated_doorbells[i] = mes->db_start_dw_offset + i * 2;
95 set_bit(i, mes->doorbell_bitmap);
103 bitmap_free(adev->mes.doorbell_bitmap);
110 adev->mes.adev = adev;
112 idr_init(&adev->mes.pasid_idr);
113 idr_init(&adev->mes.gang_id_idr);
114 idr_init(&adev->mes.queue_id_idr);
115 ida_init(&adev->mes.doorbell_ida);
116 mtx_init(&adev->mes.queue_id_lock, IPL_TTY);
117 mtx_init(&adev->mes.ring_lock, IPL_TTY);
118 rw_init(&adev->mes.mutex_hidden, "agmes");
120 adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK;
121 adev->mes.vmid_mask_mmhub = 0xffffff00;
122 adev->mes.vmid_mask_gfxhub = 0xffffff00;
128 adev->mes.compute_hqd_mask[i] = 0xc;
132 adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe;
136 adev->mes.sdma_hqd_mask[i] = i ? 0 : 0x3fc;
139 adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
141 adev->mes.sdma_hqd_mask[i] = 0xfc;
144 r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs);
150 adev->mes.sch_ctx_gpu_addr =
151 adev->wb.gpu_addr + (adev->mes.sch_ctx_offs * 4);
152 adev->mes.sch_ctx_ptr =
153 (uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs];
155 r = amdgpu_device_wb_get(adev, &adev->mes.query_status_fence_offs);
157 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
162 adev->mes.query_status_fence_gpu_addr =
163 adev->wb.gpu_addr + (adev->mes.query_status_fence_offs * 4);
164 adev->mes.query_status_fence_ptr =
165 (uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs];
167 r = amdgpu_device_wb_get(adev, &adev->mes.read_val_offs);
169 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
170 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
175 adev->mes.read_val_gpu_addr =
176 adev->wb.gpu_addr + (adev->mes.read_val_offs * 4);
177 adev->mes.read_val_ptr =
178 (uint32_t *)&adev->wb.wb[adev->mes.read_val_offs];
187 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
188 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
189 amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
191 idr_destroy(&adev->mes.pasid_idr);
192 idr_destroy(&adev->mes.gang_id_idr);
193 idr_destroy(&adev->mes.queue_id_idr);
194 ida_destroy(&adev->mes.doorbell_ida);
195 mutex_destroy(&adev->mes.mutex_hidden);
201 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
202 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
203 amdgpu_device_wb_free(adev, adev->mes.read_val_offs);
206 idr_destroy(&adev->mes.pasid_idr);
207 idr_destroy(&adev->mes.gang_id_idr);
208 idr_destroy(&adev->mes.queue_id_idr);
209 ida_destroy(&adev->mes.doorbell_ida);
210 mutex_destroy(&adev->mes.mutex_hidden);
226 /* allocate the mes process buffer */
229 DRM_ERROR("no more memory to create mes process\n");
249 amdgpu_mes_lock(&adev->mes);
251 /* add the mes process to idr list */
252 r = idr_alloc(&adev->mes.pasid_idr, process, pasid, pasid + 1,
262 process->process_quantum = adev->mes.default_process_quantum;
265 amdgpu_mes_unlock(&adev->mes);
269 amdgpu_mes_unlock(&adev->mes);
291 amdgpu_mes_lock(&adev->mes);
293 process = idr_find(&adev->mes.pasid_idr, pasid);
296 amdgpu_mes_unlock(&adev->mes);
303 spin_lock_irqsave(&adev->mes.queue_id_lock, flags);
304 idr_remove(&adev->mes.queue_id_idr, queue->queue_id);
305 spin_unlock_irqrestore(&adev->mes.queue_id_lock, flags);
310 r = adev->mes.funcs->remove_hw_queue(&adev->mes,
316 idr_remove(&adev->mes.gang_id_idr, gang->gang_id);
319 idr_remove(&adev->mes.pasid_idr, pasid);
320 amdgpu_mes_unlock(&adev->mes);
351 /* allocate the mes gang buffer */
373 amdgpu_mes_lock(&adev->mes);
375 process = idr_find(&adev->mes.pasid_idr, pasid);
382 /* add the mes gang to idr list */
383 r = idr_alloc(&adev->mes.gang_id_idr, gang, 1, 0,
397 gprops->gang_quantum : adev->mes.default_gang_quantum;
402 amdgpu_mes_unlock(&adev->mes);
406 amdgpu_mes_unlock(&adev->mes);
423 amdgpu_mes_lock(&adev->mes);
425 gang = idr_find(&adev->mes.gang_id_idr, gang_id);
428 amdgpu_mes_unlock(&adev->mes);
434 amdgpu_mes_unlock(&adev->mes);
438 idr_remove(&adev->mes.gang_id_idr, gang->gang_id);
440 amdgpu_mes_unlock(&adev->mes);
463 amdgpu_mes_lock(&adev->mes);
465 idp = &adev->mes.pasid_idr;
469 r = adev->mes.funcs->suspend_gang(&adev->mes, &input);
476 amdgpu_mes_unlock(&adev->mes);
492 amdgpu_mes_lock(&adev->mes);
494 idp = &adev->mes.pasid_idr;
498 r = adev->mes.funcs->resume_gang(&adev->mes, &input);
505 amdgpu_mes_unlock(&adev->mes);
588 /* allocate the mes queue buffer */
604 amdgpu_mes_lock(&adev->mes);
606 gang = idr_find(&adev->mes.gang_id_idr, gang_id);
613 /* add the mes gang to idr list */
614 spin_lock_irqsave(&adev->mes.queue_id_lock, flags);
615 r = idr_alloc(&adev->mes.queue_id_idr, queue, 1, 0,
618 spin_unlock_irqrestore(&adev->mes.queue_id_lock, flags);
621 spin_unlock_irqrestore(&adev->mes.queue_id_lock, flags);
634 /* add hw queue to mes */
658 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
679 amdgpu_mes_unlock(&adev->mes);
686 spin_lock_irqsave(&adev->mes.queue_id_lock, flags);
687 idr_remove(&adev->mes.queue_id_idr, queue->queue_id);
688 spin_unlock_irqrestore(&adev->mes.queue_id_lock, flags);
690 amdgpu_mes_unlock(&adev->mes);
709 amdgpu_mes_lock(&adev->mes);
711 /* remove the mes gang from idr list */
712 spin_lock_irqsave(&adev->mes.queue_id_lock, flags);
714 queue = idr_find(&adev->mes.queue_id_idr, queue_id);
716 spin_unlock_irqrestore(&adev->mes.queue_id_lock, flags);
717 amdgpu_mes_unlock(&adev->mes);
722 idr_remove(&adev->mes.queue_id_idr, queue_id);
723 spin_unlock_irqrestore(&adev->mes.queue_id_lock, flags);
732 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
740 amdgpu_mes_unlock(&adev->mes);
763 r = adev->mes.funcs->unmap_legacy_queue(&adev->mes, &queue_input);
777 op_input.read_reg.buffer_addr = adev->mes.read_val_gpu_addr;
779 if (!adev->mes.funcs->misc_op) {
780 DRM_ERROR("mes rreg is not supported!\n");
784 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
788 val = *(adev->mes.read_val_ptr);
804 if (!adev->mes.funcs->misc_op) {
805 DRM_ERROR("mes wreg is not supported!\n");
810 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
831 if (!adev->mes.funcs->misc_op) {
832 DRM_ERROR("mes reg_write_reg_wait is not supported!\n");
837 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
856 if (!adev->mes.funcs->misc_op) {
857 DRM_ERROR("mes reg wait is not supported!\n");
862 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
880 if (!adev->mes.funcs->misc_op) {
881 DRM_ERROR("mes set shader debugger is not supported!\n");
897 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
901 amdgpu_mes_lock(&adev->mes);
903 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
907 amdgpu_mes_unlock(&adev->mes);
918 if (!adev->mes.funcs->misc_op) {
919 DRM_ERROR("mes flush shader debugger is not supported!\n");
927 amdgpu_mes_lock(&adev->mes);
929 r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
933 amdgpu_mes_unlock(&adev->mes);
1007 amdgpu_mes_lock(&adev->mes);
1008 gang = idr_find(&adev->mes.gang_id_idr, gang_id);
1011 amdgpu_mes_unlock(&adev->mes);
1018 amdgpu_mes_unlock(&adev->mes);
1057 amdgpu_mes_unlock(&adev->mes);
1065 amdgpu_mes_unlock(&adev->mes);
1110 return adev->mes.aggregated_doorbells[prio];
1283 gprops.gang_quantum = adev->mes.default_gang_quantum;
1460 r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], fw_name);
1465 r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe],
1473 adev->mes.fw[pipe]->data;
1474 adev->mes.uc_start_addr[pipe] =
1477 adev->mes.data_start_addr[pipe] =
1494 info->fw = adev->mes.fw[pipe];
1501 info->fw = adev->mes.fw[pipe];
1509 amdgpu_ucode_release(&adev->mes.fw[pipe]);